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PDF AD5227 Data sheet ( Hoja de datos )
| Número de pieza | AD5227 | |
| Descripción | 64-Position Up/Down Control Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
64-position digital potentiometer
10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance
Simple up/down digital or manual configurable control
Midscale preset
Low potentiometer mode tempco = 10 ppm/°C
Low rheostat mode tempco = 35 ppm/°C
Ultralow power, IDD = 0.4 μA typ and 3 μA max
Fast adjustment time, ts = 1 μs
Chip select enable multiple device operation
Low operating voltage, 2.7 V to 5.5 V
Automotive temperature range, −40°C to +105°C
Compact thin SOT-23-8 (2.9 mm × 3 mm) Pb-free package
APPLICATIONS
Mechanical potentiometer and trimmer replacements
LCD backlight, contrast, and brightness controls
Portable electronics level adjustment
Programmable power supply
Digital trimmer replacements
Automatic closed-loop control
GENERAL DESCRIPTION
The AD5227 is Analog Devices’ latest 64-step up/down control
digital potentiometer1. This device performs the same electronic
adjustment function as a 5 V potentiometer or variable resistor.
Its simple 3-wire up/down interface allows manual switching or
high speed digital control. The AD5227 presets to midscale at
power-up. When CS is enabled, the devices changes step at
every clock pulse. The direction is determined by the state of
the U/D pin (see Table 1). The interface is simple to activate by
any host controller, discrete logic, or manually with a rotary
encoder or pushbuttons. The AD5227’s 64-step resolution, small
footprint, and simple interface enable it to replace mechanical
potentiometers and trimmers with typically 6× improved
resolution, solid-state reliability, and design layout flexibility,
resulting in a considerable cost savings in end users’ systems.
64-Position Up/Down
Control Digital Potentiometer
AD5227
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5227
CS
U/D
CLK
6-BIT UP/DOWN
CONTROL
LOGIC
A
W
B
GND
POR
MIDSCALE
WIPER
REGISTER
Figure 1.
The AD5227 is available in a compact thin SOT-23-8 (TSOT-8)
Pb-free package. The part is guaranteed to operate over the
automotive temperature range of −40°C to +105°C.
Users who consider EEMEM potentiometers should refer to
some recommendations in the Applications section.
Table 1. Truth Table
CS CLK
0↓
0↓
U/D
0
1
1X
X
Operation1
RWB Decrement
RWB Increment
No Operation
1 RWA increments if RWB decrements and vice versa.
1 The terms digital potentiometer and RDAC are used interchangeably.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703© 2004–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD5227
Parameter
Symbol
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 10)
Clock Frequency
fCLK
Input Clock Pulse Width
tCH, tCL
CS to CLK Setup Time
tCSS
CS Rise to CLK Hold Time
tCSH
U/D to Clock Fall Setup Time
tUDS
Conditions
Clock level high or low
Min Typ1 Max
50
10
10
10
10
Unit
MHz
ns
ns
ns
ns
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = V.
10 All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
VDD = 5 V.
INTERFACE TIMING DIAGRAMS
CS = LOW
U/D = HIGH
CLK
RWB
CS = LOW
U/D = 0
CLK
Figure 2. Increment RWB
RWB
Figure 3. Decrement RWB
1
CS
0
tCSS
1
CLK
0
1
U/D
0
tUDS
RWB
tCL
tS
tCH
tCSH
Figure 4. Detailed Timing Diagram (Only RWB Decrement Shown)
Rev. B | Page 4 of 16
5 Page 
AD5227
THEORY OF OPERATION
The AD5227 is a 64-position 3-terminal digitally controlled
potentiometer device. It presets to a midscale at system power-
on. When CS is enabled, changing the resistance settings is
achieved by clocking the CLK pin. It is negative-edge triggered,
and the direction of stepping is determined by the state of the
U/D input. When the wiper reaches the maximum or the
minimum setting, additional CLK pulses do not change the
wiper setting.
VDD
AD5227
CS
U/D
CLK
6-BIT UP/DOWN
CONTROL
LOGIC
A
W
B
GND
POR
MIDSCALE
WIPER
REGISTER
Figure 24. Functional Block Diagram
A
RS
D0
D1
RS
D2
D3 RS
D4
D5
RDAC
UP/DOWN
CTRL AND
DECODE
RW
W
RS
RS = RAB/64
B
Figure 25. AD5227 Equivalent RDAC Circuit
PROGRAMMING THE DIGITAL POTENTIOMETERS
Rheostat Operation
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode and is shown in Figure 26.
AAA
WWW
BBB
Figure 26. Rheostat Mode Configuration
The end-to-end resistance, RAB, has 64 contact points accessed
by the wiper terminal, plus the B terminal contact, assuming
that RWB is used (see Figure 25). Clocking the CLK input steps,
RWB by one step. The direction is determined by the state of
U/D pin. The change of RWB can be determined by the number
of clock pulses, provided that the AD5227 has not reached its
maximum or minimum scale. ΔRWB can, therefore, be
approximated as
ΔRWB
=
±⎜⎛CP ×
⎝
RAB
64
+
RW
⎟⎞
⎠
(1)
where:
CP is the number of clock pulses.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on-resistance of
the internal switch.
Since in the lowest end of the resistor string a finite wiper
resistance is present, care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switches can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened or shorted to
W. Similarly, ΔRWA can be approximated as
ΔRWA
=
±⎜⎝⎛ (64
− CP ) RAB
64
+
RW
⎟⎠⎞
(2)
Equations 1 and 2 do not apply when CP = 0.
The typical distribution of the resistance tolerance from device
to device is process lot dependent. It is possible to have ±20%
tolerance.
Potentiometer Mode Operation
If all three terminals are used, the operation is called
potentiometer mode. The most common configuration is the
voltage divider operation as shown in Figure 27.
VI A
VC
W
B
Figure 27. Potentiometer Mode Configuration
Rev. B | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD5227.PDF ] | |
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