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AD5689R の電気的特性と機能

AD5689RのメーカーはAnalog Devicesです、この部品の機能は「Dual 16-/12-Bit nanoDAC+」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD5689R
部品説明 Dual 16-/12-Bit nanoDAC+
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD5689R Datasheet, AD5689R PDF,ピン配置, 機能
Data Sheet
Dual, 16-/12-Bit nanoDAC+
with 2 ppm/°C Reference, SPI Interface
AD5689R/AD5687R
FEATURES
High relative accuracy (INL): ±2 LSB maximum at 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD ratings
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5689R/AD5687R members of the nanoDAC+™
family are low power, dual, 16-/12-bit buffered voltage output
digital-to-analog converters (DACs). The devices include
a 2.5 V, 2 ppm/°C internal reference (enabled by default)
and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic
by design, and exhibit less than 0.1% FSR gain error and
1.5 mV offset error performance. Both devices are available
in a 3 mm × 3 mm LFCSP and a TSSOP package.
The AD5689R/AD5687R also incorporate a power-on reset
circuit and a RSTSEL pin that ensure that the DAC outputs
power up to zero scale or midscale and remain there until
a valid write takes place. Each part contains a per channel
power-down feature that reduces the current consumption
of the device to 4 µA at 3 V while in power-down mode.
The AD5689R/AD5687R use a versatile serial peripheral
interface (SPI) that operates at clock rates up to 50 MHz.
and both devices contain a VLOGIC pin that is intended for
1.8 V/3 V/5 V logic.
VLOGIC
SCLK
SYNC
SDIN
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
AD5689R/AD5687R
2.5V
REFERENCE
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
BUFFER
VOUT A
VOUT B
SDO
LDAC RESET
POWER-ON
RESET
GAIN =
×1/×2
RSTSEL
Figure 1.
GAIN
POWER-
DOWN
LOGIC
Table 1. Dual nanoDAC+ Devices
Interface
Reference
16-Bit
SPI
Internal
AD5689R
External
AD5689
I2C
Internal
N/A
External
N/A
12-Bit
AD5687R
AD5687
AD5697R
N/A
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5689R (16-bit): ±2 LSB maximum
AD5687R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





AD5689R pdf, ピン配列
Data Sheet
AD5689R/AD5687R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE2
AD5689R
Resolution
Relative Accuracy
Differential
Nonlinearity
AD5687R
Resolution
Relative Accuracy
Differential
Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error
Offset Error Drift3
Gain Temperature
Coefficient3
DC Power Supply
Rejection Ratio3
DC Crosstalk3
Min
16
12
OUTPUT CHARACTERISTICS3
Output Voltage Range
Capacitive Load Stability
0
0
Resistive Load4
Load Regulation
1
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
A Grade1
Typ Max
Min
±2 ±8
±2 ±8
±1
16
±0.12 ±2
±1
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
4
±4
±0.2
±0.2
±0.25
±0.25
0.15
12
±2
±3
±2
VREF
2 × VREF
2
10
80
80
40
25
2.5
0
0
1
B Grade1
Typ Max
Unit Test Conditions/Comments
±1 ±2
±1 ±3
±1
Bits
LSB Gain = 2
Gain = 1
LSB Guaranteed monotonic by design
±0.12 ±1
±1
0.4
+0.1
+0.01
±0.02
±0.01
±1
±1
1.5
±1.5
±0.1
±0.1
±0.1
±0.2
0.15
±2
±3
±2
VREF
2 × VREF
2
10
80
80
40
25
2.5
Bits
LSB
LSB Guaranteed monotonic by design
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
ppm
All 0s loaded to DAC register
All 1s loaded to DAC register
External reference; gain = 2; TSSOP
Internal reference; gain = 1; TSSOP
Of FSR/°C
mV/V
DAC code = midscale;
VDD = 5 V ± 10%
µV
µV/mA
µV
Due to single channel, full-scale
output change
Due to load current change
Due to powering down
(per channel)
V
V
nF
nF
kΩ
µV/mA
µV/mA
mA
Ω
µs
Gain = 1
Gain = 2, see Figure 31
RL = ∞
RL = 1 kΩ
5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ 30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ 20 mA
See Figure 31
Coming out of power-down
mode; VDD = 5 V
Rev. A | Page 3 of 28


3Pages


AD5689R 電子部品, 半導体
AD5689R/AD5687R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Power-Up Time
1.8 V ≤ VLOGIC < 2.7 V
Min Max
33
16
16
15
5
5
15
20
2.7 V ≤ VLOGIC 5.5 V
Min Max
20
10
10
10
5
5
10
20
16 10
25 15
30 20
20 20
30 30
30 30
4.5 4.5
Unit Description
ns SCLK cycle time
ns SCLK high time
ns SCLK low time
ns SYNC to SCLK falling edge setup time
ns Data setup time
ns Data hold time
ns SCLK falling edge to SYNC rising edge
ns Minimum SYNC high time (update single channel or both
channels)
ns SYNC falling edge to SCLK fall ignore
ns LDAC pulse width low
ns SCLK falling edge to LDAC rising edge
ns SCLK falling edge to LDAC falling edge
ns RESET minimum pulse width low
ns RESET pulse activation time
µs Time that is required to exit power-down and enter normal mode
of operation; 24th clock edge to 90% of DAC midscale value with
output unloaded
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
SCLK
SYNC
SDIN
LDAC1
LDAC2
RESET
t9 t1
t8 t4
t3
DB23
t6
t5
t2 t7
DB0
t12
t10
t11
t13
VOUTX
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 6 of 28

6 Page



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部品番号部品説明メーカ
AD5689

Dual 16-/12-Bit nanoDAC+

Analog Devices
Analog Devices
AD5689R

Dual 16-/12-Bit nanoDAC+

Analog Devices
Analog Devices


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