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PDF ISL68127 Data sheet ( Hoja de datos )
| Número de pieza | ISL68127 | |
| Descripción | PWM Controller | |
| Fabricantes | Intersil Corporation | |
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DATASHEET
Digital Dual Output, 7-Phase Configurable, PWM
Controller with PMBus
ISL68127
The ISL68127 is a digital dual output, flexible multiphase
(X+Y ≤ 7) PWM controller supporting the latest PMBus 1.3
specifications. Either output can be configured to support any
desired phase assignments up to a maximum of seven phases
across the two outputs (X+Y). For example, 6+1, 5+2, 4+2,
3+3, 3+2, or even a single output operation as a 7+0
configuration are supported. The ISL68127 utilizes Intersil’s
proprietary linear synthetic digital current modulation scheme
to achieve the industry’s best combination of transient
response and ease of tuning while addressing the challenges
of modern multiphase designs.
Device configuration and telemetry monitoring is
accomplished using Intersil's intuitive PowerNavigator™ GUI.
The ISL68127 device supports on-chip nonvolatile memory to
store various configuration settings that are user-selectable via
pin-strap, giving system designers increased power density to
configure and deploy multiple configurations. The device
supports an automatic phase add/drop feature to allow
maximum efficiency across all load ranges. Thresholds for
automatic phase add/drop are user-programmable using the
powerful PowerNavigator™ GUI.
The ISL68127 supports a comprehensive fault management
system to enable the design of highly reliable systems. From a
multitiered overcurrent protection scheme, to the configurable
power-good and output overvoltage/undervoltage fault
thresholds and temperature monitoring, virtually any need is
accommodated.
With minimal external components, easy configuration, robust
fault management, and highly accurate regulation capability,
implementing a high-performance, multiphase regulator has
never been easier.
Applications
• Networking equipment
• Telecom/datacom equipment
• Server/storage equipment
• Point-of-load power supply (Memory, DSP, ASIC, FPGA)
Features
• Advanced linear digital modulation scheme
- Zero latency synthetic current control for excellent HF
current balance
- Dual edge modulation for fastest transient response
• Auto phase add/drop for excellent load vs efficiency profile
• PMBus 1.3 support
- Telemetry - VIN, VOUT, IOUT, power IN/OUT, temperature,
and various fault status registers
- Up to 1MHz bus interface
• Flexible phase configuration
- 7+0, 6+1, 5+2, 4+3 phase operation
- Operation using less than 7 phases between 2 outputs is
also supported
• Diode braking for overshoot reduction
• Differential remote voltage sensing supports 0.5% closed
loop system accuracy over load, line and temperature
• Highly accurate current sensing for excellent load line
regulation and accurate OCP
- Supports the ISL99227 60A smart power stage
- Supports DCR sense with integrated temperature
compensation
• Comprehensive fault management enables high reliability
systems
- Pulse-by-pulse phase current limiting
- Total output current protection
- Output and input OV/UV
- Open voltage sense detect
- Black box recording capability for faults
• Intuitive configuration via PowerNavigator™ GUI
- NVM to store up to eight configurations
• Pb-free (RoHS compliant)
Related Literature
• For a full list of related documents, visit our web page
- ISL68127 product page
September 28, 2016
FN8748.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2016. All Rights Reserved
Intersil (and design) and PowerNavigator are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Internal Block Diagram
ISL68127
CS0
CSRTN0
CS1
CSRTN1
CS2
CSRTN2
CS3
CSRTN3
CS4
CSRTN4
CS5
CSRTN6
CS6
CSRTN6
ADC
ADC
ADC
ADC
ADC
ADC
ADC
VDROOP
VSEN0
RGND0
VSA
ADC
VDROOP
VSEN1
RGND1
VSA
ADC
VINSEN
TMON0
TMON1
VCC
VR12
LDO
CURRENT
AC FB
PID
CURRENT
AC FB
PID
ADC
CYCLE-
CYCLE OCP
CYCLE-
CYCLE OCP
CYCLE-
CYCLE OCP
CYCLE-
CYCLE OCP
CYCLE-
CYCLE OCP
CYCLE-
CYCLE OCP
CYCLE-
CYCLE OCP
SUMMED
OCP
SUMMED
OCP
OV ‐
+
-
UV +
OV -
+
-
UV +
FAULT AND
TELEMETRY
MANAGER
STATUS
MANAGER
LOOP
MANAGER
CPU
NVM
BLACKBOX
DIGITAL
DUAL EDGE
MODULATOR
DIGITAL
DUAL EDGE
MODULATOR
PMBUS
INTERFACE
FIGURE 1. INTERNAL BLOCK DIAGRAM
PG0
PG1
TWARN
EN0
EN1
CONFIG
SA
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
SCL
SDA
SALRT
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5
FN8748.0
September 28, 2016
5 Page 
ISL68127
Electrical Specifications Recommended operating conditions, VCC = 3.3V, unless otherwise specified. Boldface limits apply across the
operating temperature range -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNIT
DIGITAL DROOP
Droop Resolution
0.01 mV/A
OSCILLATORS
Accuracy of Switching Frequency Setting
When set to 500kHz
480 500 520 kHz
-4 +4 %
Switching Frequency Range
200 1000 kHz
SOFT-START RATE AND VOLTAGE TRANSITION RATE
Minimum Soft-Start Ramp Rate
Programmable minimum rate
20 µs
Maximum Soft-Start Ramp Rate
Programmable maximum rate
10 ms
Soft-Start Ramp Rate Accuracy
-4 4 %
Minimum Transition Rate
Programmable minimum rate
0.1 mV/µs
Maximum Transition Rate
Programmable maximum rate
100 mV/µs
Transition Rate Accuracy
-4 4 %
PWM OUTPUT
PWMx Output High Level
PWMx Output Low Level
PWMx Output Tri-State IOL
PWMx Output Tri-State IOH
THERMAL MONITORING AND PROTECTION
IOUT = 4mA
IOUT = 4mA
VOH = VCC
VOL = 0V
VCC - 0.4
-1
V
0.4 V
1 µA
µA
Temperature Sensor Range
-50 150 °C
Temperature Sensor Accuracy
TMON to ADC accuracy
-4.5 4.5 %
TWARN Output Low Impedance
4 9 13 Ω
TWARN Hysteresis
3 °C
POWER-GOOD AND PROTECTION MONITORS
PG Output Low Voltage
PG Leakage Current
IOUT = 8mA load
With pull-up resistor externally connected to VCC
0.4 V
0.5 1 µA
Overvoltage Protection Threshold Resolution
1 mV
Undervoltage Protection Threshold Resolution
1 mV
Overvoltage Protection Threshold When Disabled
INPUT VOLTAGE SENSE
VCC - 0.2
V
Input Voltage Accuracy
VINSEN to ADC accuracy
-2.5 2.5 %
Input Voltage Protection Threshold Resolution
1 mV
SMBus/PMBus
SALERT, SDA Output Low Level
SCL, SDA Input High/Low Threshold
IOUT = 4mA
1.25
0.4
V
V
SCL, SDA Input Hysteresis
2 mV
SCL Frequency Range
0.05
2 MHz
NOTES:
6. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Submit Document Feedback 11
FN8748.0
September 28, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL68127.PDF ] | |
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