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IDT70V9089 の電気的特性と機能

IDT70V9089のメーカーはIDTです、この部品の機能は「HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IDT70V9089
部品説明 HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM
メーカ IDT
ロゴ IDT ロゴ 




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IDT70V9089 Datasheet, IDT70V9089 PDF,ピン配置, 機能
HIGH-SPEED 3.3V
64/32K x 8 SYNCHRONOUS
Š DUAL-PORT STATIC RAM
IDT70V9089/79S/L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 12ns (max.)
Low-power operation
– IDT70V9089/79S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9089/79L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in the Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
FT/PIPER
,
I/O0R - I/O7R
A15L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. A15X is a NC for IDT70V9079.
Counter/
Address
Reg.
©2014 Integrated Device Technology, Inc.
MEMORY
ARRAY
1
Counter/
Address
Reg.
A15R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3750 drw 01
JULY 2014
DSC 3750/12

1 Page





IDT70V9089 pdf, ピン配列
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
Chip Enables
Read/Write Enable
OEL
A0L - A15L(1)
OER
A0R - A15R(1)
Output Enable
Address
I/O0L - I/O7L
CLKL
I/O0R - I/O7R
CLKR
Data Input/Output
Clock
ADSL
CNTENL
CNTRSTL
FT/PIPEL
ADSR
CNTENR
CNTRSTR
FT/PIPER
VDD
VSS
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (3.3V)
Ground (0V)
3750 tbl 01
NOTE:
1. A15X is a NC for IDT70V9079.
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
Truth Table I—Read/Write and
Enable Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-7
Mode
X H X X High-Z Deselected - Power Down
X X L X High-Z Deselected - Power Down
X L H L DATAIN Write
L L H H DATAOUT Read
HX L H X
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
3750 tbl 02
Truth Table II—Address Counter Control(1,2,3)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS CNTEN CNTRST
I/O(3)
MODE
An X An L(4) X H DI/O (n) External Address Used
X
An
An + 1
H
L(5)
H DI/O(n+1) Counter Enabled—Internal Address generation
X
An + 1 An + 1
H
H
H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
X
A0 X X
L(4) DI/O(0) Counter Reset to Address 0
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
3750 tbl 03
6.432


3Pages


IDT70V9089 電子部品, 半導体
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)(Cont'd)
70V9089/79X12 70V9089/79X15
Com'l & Ind
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4) Max. Typ.(4) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIL
Outputs Disabled
f = fMAX(1)
COM'L S 150 240 130 220 mA
L 150 215 130 185
IND
S ____ ____ ____ ____
L 150
215
____
____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(1)
COM'L S 40 65 30 55 mA
L 40 60 30 35
IND
S ____ ____ ____ ____
L 40 60 ____ ____
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
COM'L S 100
160
90
150 mA
CE"B" = VIH(3)
L 100
140
90
130
Active Port Outputs Disabled,
f=fMAX(1)
IND
S ____ ____ ____ ____
L 100
150
____
____
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VDD - 0.2V
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L S 1.0 5 1.0 5 mA
L 0.4 3 0.4 3
IND
S ____ ____ ____ ____
L 0.4 3 ____ ____
ISB4 Full Standby Current
CE"A" < 0.2V and
COM'L S 90 150 80 140 mA
(One Port -
CE"B" > VDD - 0.2V(5)
L 90 130 80 120
CMOS Level Inputs)
VIN > VDD - 0.2V or
VIN < 0.2V, Active Port
IND
S ____ ____ ____ ____
Outputs Disabled, f = fMAX(1)
L 90 140 ____ ____
3750 tbl 09b
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.462

6 Page



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共有リンク

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部品番号部品説明メーカ
IDT70V9089

HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT
IDT
IDT70V9089L

HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT
IDT
IDT70V9089S

HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT
IDT


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