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IDT70V7599S の電気的特性と機能

IDT70V7599SのメーカーはIDTです、この部品の機能は「HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IDT70V7599S
部品説明 HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
メーカ IDT
ロゴ IDT ロゴ 




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IDT70V7599S Datasheet, IDT70V7599S PDF,ピン配置, 機能
HIGH-SPEED 3.3V 128K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
IDT70V7599S
Features:
128K x 36 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
64 independent 2K x 36 banks
– 4 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
CONTROL
LOGIC
I/O0L-35L
I/O
CONTROL
A10L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2015 Integrated Device Technology, Inc.
MUX
2Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 1)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
1
TMS
TCK
TRST
CONTROL
LOGIC
I/O
CONTROL
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
I/O0R-35R
ADDRESS
DECODE
BANK
DECODE
A10R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5626 drw 01
,
JUNE 2015
DSC 5626/7

1 Page





IDT70V7599S pdf, ピン配列
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Pin Configuration(1,2,3,4) (con't.)
Industrial and Commercial Temperature Ranges
70V7599BC
BC256(5)
A1 A2
A3 A4
NC TDI NC NC
256-Pin BGA
Top View(6)
A5
A6 A7
A8 A9
A10 A11 A12
A13 A14 A15 A16
BA3L BA0L A8L BE2L CE1L OEL CNTENL A5L A2L A0L NC NC
B1
B2
B3
B4
B5 B6
B7
B8 B9
B10 B11
B12 B13 B14 B15 B16
I/O18L NC TDO NC BA4L BA1L A9L BE3L CE0L R/WL REPEATL A4L A1L VDD I/O17L NC
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16
I/O18R I/O19L VSS BA5L BA2L A10L A7L BE1L BE0L CLKL ADSL A6L A3L OPTL I/O17R I/O16L
D1 D2 D3 D4
D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15 D16
I/O20R I/O19R I/O20L PL/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E1
E2
E3
E4
E5
E6 E7
E8
E9
E10 E11
E12 E13
E14 E15 E16
I/O21R I/O21L I/O22L VDDQL VDD VDD VSS VSS VSS VSS VDD VDD VDDQR I/O13L I/O14L I/O14R
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16
I/O23L I/O22R I/O23R VDDQL VDD VSS VSS VSS VSS VSS VSS VDD VDDQR I/O12R I/O13R I/O12L
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16
I/O24R I/O24L I/O25L VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL I/O10L I/O11L I/O11R
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16
I/O26L I/O25R I/O26R VDDQR VSS VSS VSS VSS VSS VSS VSS VSS VDDQL I/O9R IO9L I/O10R
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16
I/O27L I/O28R I/O27R VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR I/O8R I/O7R I/O8L
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16
I/O29R I/O29L I/O28L VDDQL VSS VSS VSS VSS VSS VSS VSS VSS VDDQR I/O6R I/O6L I/O7L
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16
I/O30L I/O31R I/O30R VDDQR VDD VSS VSS VSS VSS VSS VSS VDD VDDQL I/O5L I/O4R I/O5R
M1 M2 M3 M4
M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
I/O32R I/O32L I/O31L VDDQR VDD VDD VSS VSS VSS VSS VDD VDD VDDQL I/O3R I/O3L I/O4L
N1 N2 N3 N4
N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16
I/O33L I/O34R I/O33R PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDD I/O2L I/O1R I/O2R
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16
I/O35R I/O34L TMS BA5R BA2R A10R A7R BE1R BE0R CLKR ADSR A6R A3R I/O0L I/O0R I/O1L
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16
I/O35L NC TRST NC BA4R BA1R A9R BE3R CE0R R/WR REPEATR A4R A1R OPTR NC NC
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
NC TCK NC NC BA3R BA0R A8R BE2R CE1R OER CNTENR A5R A2R A0R NC NC
NOTES:
5626 drw 02d
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.432


3Pages


IDT70V7599S 電子部品, 半導体
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3,4)
OE3 CLK CE0 CE1 BE3 BE2 BE1 BE0 R/W
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X H X X X X X X High-Z High-Z High-Z High-Z Deselected–Power Down
X X L X X X X X High-Z High-Z High-Z High-Z Deselected–Power Down
X L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected
X L H H H H L L High-Z High-Z High-Z
DIN Write to Byte 0 Only
X L H H H L H L High-Z High-Z DIN High-Z Write to Byte 1 Only
X L H H L H H L High-Z DIN High-Z High-Z Write to Byte 2 Only
X L H L H H H L DIN High-Z High-Z High-Z Write to Byte 3 Only
X L H H H L L L High-Z High-Z
DIN
DIN Write to Lower 2 Bytes Only
XL HL L HHL
DIN
DIN High-Z High-Z Write to Upper 2 bytes Only
XLHL L L L L
DIN
DIN
DIN
DIN Write to All Bytes
L L H H H H L H High-Z High-Z High-Z DOUT Read Byte 0 Only
L L H H H L H H High-Z High-Z DOUT High-Z Read Byte 1 Only
L L H H L H H H High-Z DOUT High-Z High-Z Read Byte 2 Only
L L H L H H H H DOUT High-Z High-Z High-Z Read Byte 3 Only
L L H H H L L H High-Z High-Z DOUT
DOUT Read Lower 2 Bytes Only
L L H L L H H H DOUT
DOUT High-Z High-Z Read Upper 2 Bytes Only
L L H L L L L H DOUT
DOUT
DOUT
DOUT Read All Bytes
H X X X X X X X X High-Z High-Z High-Z High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refers to Truth Table II for details.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5626 tbl 02
Truth Table II—Address and Address Counter Control(1,2,7)
Previous Addr
Address Address Used CLK ADS CNTEN REPEAT(6)
I/O(3)
MODE
An
X An L(4) X
H DI/O (n) External Address Used
X
An An + 1 H L(5)
H DI/O(n+1) Counter Enabled—Internal Address generation
X An + 1 An + 1 H H
H DI/O(n+1) External Addre ss Blocked—Counter disab led (An + 1 reused)
X
X
An X
X
L(4) DI/O(0) Counter Set to last valid ADS load
NOTES:
5626 tbl 03
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L
- BA5L BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.
6.462

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部品番号部品説明メーカ
IDT70V7599S

HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

IDT
IDT


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