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What is IDT70V3599S?

This electronic component, produced by the manufacturer "Integrated Device Technology", performs the same function as "HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM".


IDT70V3599S Datasheet PDF - Integrated Device Technology

Part Number IDT70V3599S
Description HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
Manufacturers Integrated Device Technology 
Logo Integrated Device Technology Logo 


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HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V3599/89S
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
BE3R
BE2R
BE1R
BE0R
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a
1/0
a
0b 1b
b
0c 1c
c
0d 1d
d
1
0
1/0
BB BBBB BB
WW WWWW WW
01 2332 10
L L L L RR RR
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
a b cd
I/O0L - I/O35 L
CLKL
A16L(1)
A0L
REPEATL
ADSL
CNTENL
NOTE:
1. A16 is a NC for IDT70V3589.
©2003 Integrated Device Technology, Inc.
Counter/
Address
Reg.
TDI
TDO
128K x 36
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
JTAG
1
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
1
0
1 /0
FT/PIPER
R/WR
CE0R
CE1R
OER
0a 1a 0b 1b 0c 1c 0d 1d
d cba
0/1
FT/PIPER
Counter/
Address
Reg.
TCK
TMS
TRST
I/O0R - I/O35R
CLKR
A 16 R( 1)
A0R
REPEATR
ADSR
CNTENR
,
5617 tbl 01
MAY 2003
DSC 5617/6

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IDT70V3599S equivalent
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A16L(1)
OER
A0R - A16R(1)
I/O0L - I/O35L
CLKL
PL/FTL
I/O0R - I/O35R
CLKR
PL/FTR
ADSL
ADSR
CNTENL
CNTENR
REPEATL
REPEATR
BE0L - BE3L
VDDQL
OPTL
BE0R - BE3R
VDDQR
OPTR
VDD
VSS
TDI
TDO
TCK
TMS
TRST
Names
Chip Enables(5)
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat(4)
Byte Enables (9-bit bytes)(5)
Power (I/O Bus) (3.3V or 2.5V)(2)
Option for selecting VDDQX(2,3)
Power (3.3V)(2)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5617 tbl 01
NOTES:
1. A16 is a NC for IDT70V3589.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
65.42


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Featured Datasheets

Part NumberDescriptionMFRS
IDT70V3599The function is HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM. Integrated Device TechnologyIntegrated Device Technology
IDT70V3599SThe function is HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM. Integrated Device TechnologyIntegrated Device Technology

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