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PDF IDT709079S Data sheet ( Hoja de datos )
| Número de pieza | IDT709079S | |
| Descripción | HIGH-SPEED 32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 32K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM
PRELIMINARY
IDT709079S/L
Features:
◆ True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆ High-speed clock to data access
– Commercial: 9/12/15ns (max.)
– Industrial: 12ns (max.)
◆ Low-power operation
– IDT709079S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709079L
Active: 950mW (typ.)
Standby: 1mW (typ.)
◆ Flow-Through or Pipelined output mode on either port via
the FT/PIPER pin
◆ Counter enable and reset features
◆ Dual chip enables allow for depth expansion without
additional logic
◆ Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in the Pipelined
output mode
◆ TTL- compatible, single 5V (±10%) power supply
◆ Industrial temperature range (–40°C to +85°C) is
available for selected speeds
◆ Available in a 100 pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
OEL
R/WR
OER
CE0L
CE1L
1
0
0/1
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
FT/PIPER
I/O0R - I/O7R
A14L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A14R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3495 drw 01
DECEMBER 2002
©2002 Integrated Device Technology, Inc.
1
DSC 3495/8
1 page  
IDT709079S/L
High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Teamperature and Supply Voltage Range (VCC = 5.0V ± 10%)
Symbol
|ILI|
Parameter
Input Leakage Current(1)
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
709079S/L
Min. Max.
___ 10
Unit
µA
|ILO| Output Leakage Current
VOL Output Low Voltage
VOH Output High Voltage
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
CE0 = VIH or CE1 = VIL, VOUT = 0V to VCC
IOL = +4mA
IOH = -4mA
___ 10 µA
___ 0.4 V
2.4 ___ V
3495 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VCC = 5V ± 10%)
709079X9
Com'l Only
709079X12
Com'l
& Ind
709079X15
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIH,
Outputs Disabled
f = fMAX(1)
COM'L S 210 390 200 345 190 325 mA
L 210 350 200 305 190 285
IND S ____ ____ 200 380 ____ ____
L ____ ____ 200 340 ____ ____
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(1)
COM'L S 50 135 50 110 50 110 mA
L 50 115 50 90 50 90
IND S ____ ____ 50 125 ____ ____
L ____ ____ 50 105 ____ ____
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
COM'L S 140 270 130 230 120 220 mA
CE"B" = VIH(3)
L 140 240 130 200 120 190
Active Port Outputs Disabled,
f=fMAX(1)
IND S ____ ____ 130 245 ____ ____
L ____ ____ 130 215 ____ ____
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L S 1.0 15 1.0 15 1.0 15 mA
L 0.2 5 0.2 5 0.2 5
IND S ____ ____ 1.0 15 ____ ____
L ____ ____ 0.2 5 ____ ____
ISB4 Full Standby Current
CE"A" < 0.2V and
COM'L S 130 245 120 205 110 195 mA
(One Port -
CE"B" > VCC - 0.2V(5)
L 130 225 120 185 110 175
CMOS Level Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V
IND S ____ ____ 120 220 ____ ____
Active Port Outputs Disabled
L ____ ____ 120 200 ____ ____
f = fMAX(1)
NOTES:
3495 tbl 09
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.452
5 Page 
IDT709079S/L
High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
tSC tHC
R/W
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
(2)
An +1
tCD2
READ
An + 2
An + 2
tSD tHD
An + 3
Dn + 2
tCKHZ (1)
Qn
NOP(5)
WRITE
An + 4
tCKLZ(1) tCD2
Qn + 3
READ
3495 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC tHC
CE1
R/W
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
(2)
An +1
An + 2
tSD tHD
Dn + 2
tCD2
Qn
tOHZ(1)
An + 3
Dn + 3
An + 4
An + 5
tCKLZ(1)
tCD2
Qn + 4
OE
READ
WRITE
READ
3495 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1412
11 Page | ||
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