DataSheet.jp

IDT709099L の電気的特性と機能

IDT709099LのメーカーはIDTです、この部品の機能は「HIGH-SPEED 128K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IDT709099L
部品説明 HIGH-SPEED 128K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
メーカ IDT
ロゴ IDT ロゴ 




このページの下部にプレビューとIDT709099Lダウンロード(pdfファイル)リンクがあります。
Total 16 pages

No Preview Available !

IDT709099L Datasheet, IDT709099L PDF,ピン配置, 機能
HIGH-SPEED 128K x 8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709099L
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT709099L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66.7MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O7L
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O7R
A16R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4846 drw 01
©2015 Integrated Device Technology, Inc.
1
APRIL 2015
DSC-4846/8

1 Page





IDT709099L pdf, ピン配列
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
OEL
A0L - A16L
I/O0L - I/O7L
CLKL
ADSL
CNTENL
CNTRSTL
FT/PIPEL
CE0R, CE1R
R/WR
OER
A0R - A16R
I/O0R - I/O7R
CLKR
ADSR
CNTENR
CNTRSTR
FT/PIPER
VCC
GND
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power
Ground
4846 tbl 01
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-7
X HX X
High-Z
Deselected—Power Down
XX LX
High-Z
Deselected—Power Down
XL HL
DATAIN
Write
LL HH
DATAOUT
Read
HX L HX
High-Z
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Mode
4846 tbl 02
Truth Table II—Address Counter Control(1,2,6)
Previous
Address Address
Addr
Used
CLK ADS CNTEN CNTRST
I/O(3)
Mode
XX
0
X
X
L
DI/O(0) Counter Reset to Address 0
An X An L(4) X H DI/O(n) External Address Utilized
An Ap Ap H H H DI/O(n) External Address Blocked—Counter Disabled (Ap reused)
X
Ap
Ap + 1
H
L(5) H
DI/O(n+1) Counter Enable—Internal Address Generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
4846 tbl 03
6.342


3Pages


IDT709099L 電子部品, 半導体
IDT709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1,2 and 3
4846 tbl 10
Industrial and Commercial Temperature Ranges
DATAOUT
347
5V
893
30pF
DATAOUT
347
5V
893
5pF*
4846 drw 04
Figure 1. AC Output Test load.
4846 drw 05
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
tCD1,
tCD2
(Typical, ns)
8
7
6
5
4
3
2
1
0
-1
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
4846 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.642

6 Page



ページ 合計 : 16 ページ
 
PDF
ダウンロード
[ IDT709099L データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IDT709099L

HIGH-SPEED 128K x 8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT
IDT


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap