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Número de pieza | TX13D06VM2BPA | |
Descripción | Display Module | |
Fabricantes | Hitachi | |
Logotipo | ||
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DATE : Jan 25th, 2013
CUSTOMER’S ACCEPTANCE SPECIFICATIONS
TX13D06VM2BPA
Contents
No. ITEM
1 COVER
2 RECORD OF REVISION
3 GENERAL DATA
4 ABSOLUTE MAXIMUM RATINGS
5 ELECTRICAL CHARACTERISTICS
6 OPTICAL CHARACTERISTICS
7 BLOCK DIAGRAME
8 RELIABILITY TESTS
9 LCD INTERFACE
10 OUTLINE DIMENSIONS
11 TOUCH PANEL
12 APPEARANCE STANDARD
13 PRECAUTIONS
14 DESIGNATION OF LOT MARK
SHEET No.
7B64PS 2701-TX13D06VM2BPA-1
7B64PS 2702-TX13D06VM2BPA-1
7B64PS 2703-TX13D06VM2BPA-1
7B64PS 2704-TX13D06VM2BPA-1
7B64PS 2705-TX13D06VM2BPA-1
7B64PS 2706-TX13D06VM2BPA-1
7B64PS 2707-TX13D06VM2BPA-1
7B64PS 2708-TX13D06VM2BPA-1
7B64PS 2709-TX13D06VM2BPA-1
7B64PS 2710-TX13D06VM2BPA-1
7B64PS 2711-TX13D06VM2BPA-1
7B64PS 2712-TX13D06VM2BPA-1
7B64PS 2713-TX13D06VM2BPA-1
7B64PS 2714-TX13D06VM2BPA-1
PAGE
1-1/1
2-1/1
3-1/1
4-1/1
5-1/1
6-1/2~2/2
7-1/1
8-1/1
9-1/8~8/8
10-1/2~2/2
11-1/2~2/2
12-1/3~3/3
13-1/2~2/2
14-1/1
ACCEPTED BY:
KAOHSIUNG OPTO-ELECTRONICS INC.
SHEET
NO.
PROPOSED BY:
7B64PS 2701-TX13D06VM2BPA-1
PAGE 1-1/1
1 page 5. ELECTRICAL CHARACTERISTICS
5.1 LCD CHARACTERISTICS
Ta 25 C, VSS 0V
Item
Symbol
Condition
Min.
Typ.
Max.
Unit Remarks
Power Supply Voltage
Input Voltage of Logic
Power Supply Current
Vsync Frequency
Hsync Frequency
DCLK Frequency
VDD
VI
IDD
fv
fH
fCLK
-
“H” level
“L” level
-
-
-
-
3.0
0.8VDD
VSS
-
55
28.9
30.5
3.3
-
-
120
60
31.5
33.3
3.6
VDD
0.2VDD
140
65
34.1
36.0
V
V
mA
Hz
KHz
MHz
-
Note 1
Note 2
-
-
-
Note 1: The rating is defined for the signal voltages of the interface such as DE, Hsync, Vsync, CLK
and RGB data bus.
Note 2: An all black check pattern is used when measuring IDD, fv is set to 60 Hz.
Note 3: 0.75A fuse is applied in the module for IDD. For display activation and protection purpose,
power supply is recommended larger than 2A to start the display and break fuse once any
short circuit occurred.
5.2 BACKLIGHT CHARACTERISTICS
Item
LED Input Voltage
LED Forward Current
LED Lifetime
Symbol
VLED
ILED
-
Condition
Backlight Unit
Backlight Unit
192 mA
Min.
11.5
-
-
Typ. Max.
12.0
12.5
192 -
50K -
Ta 25 C
Unit Remarks
V Note1
mA -
hrs Note 2
Note 1: Fig. 5.1 shows the backlight circuit of two LED bars.
Note 2: The estimated lifetime is specified as the time to reduce 50% brightness by applying 192 mA at
25 C .
VLED(+)
6 Parallel
16mA/ per LED
VLED(-)
Fig. 5.1
KAOHSIUNG OPTO-ELECTRONICS INC.
SHEET
NO.
7B64PS 2705-TX13D06VM2BPA-1
PAGE 5-1/1
5 Page 9.2 TIMING CHART
1) Sync Mode ( the DE pin pulled low)
Fig. 9.1 Horizontal Timing of Synchronous Mode
Note 1: CLK’s falling edge is the time to latch data and count (thp + thb), therefore, data sending and
Hsync’s falling edge should start when CLK’s rise edge.
Fig. 9.2 Vertical Timing of Synchronous Mode
Note 2: Vsync’s falling edge needs to start with Hsync’s falling edge simultaneously to count (tvp + tvb)
KAOHSIUNG OPTO-ELECTRONICS INC.
SHEET
NO.
7B64PS 2709-TX13D06VM2BPA-1
PAGE 9-2/8
11 Page |
Páginas | Total 28 Páginas | |
PDF Descargar | [ Datasheet TX13D06VM2BPA.PDF ] |
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