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UPD8085A-2 の電気的特性と機能

UPD8085A-2のメーカーはNECです、この部品の機能は「Single Chip 8-BIT N-CHANNEL MICROPROCESSOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD8085A-2
部品説明 Single Chip 8-BIT N-CHANNEL MICROPROCESSOR
メーカ NEC
ロゴ NEC ロゴ 




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UPD8085A-2 Datasheet, UPD8085A-2 PDF,ピン配置, 機能
NEe Microcomputers, Inc.
fLPD8085A SINGLE CHIP 8·BIT
N·CHANNEL MICROPROCESSOR
NEe
JLPD8085A
JLPD8085A-2
DESC RIPT ION
The j.LPD8085A is a single chip B-bit microprocessor which is 100 percent software
compatible with the industry standard 8080A_ It has the ability of increasing system
performance of the industry standard 8080A by operating at a higher speed. Using
the j.LPD80B5A in conjunction with its family of ICs allows the designer complete
flexibility with minimum chip count.
FEATURES
Single Power Supply: +5Volt,±10%
• Internal Clock Generation and
System Control
• Internal Serial In/Out Port.
• Fully TTL Compatible
• Internal 4-Level Interrupt Structure
• Multiplexed Address/Data Bus for
Increased System Performance
• Complete Family of Components for
Design Flexibility
• Software Compatible with Industry Standard 8080A
• Higher Throughput: j.LPD8085A - 3 MHz
j.LPD80B5A-2 - 5 MHz
• Available in Either Plastic or Ceramic Package
PIN CONFIGURATION
Xl
X2
RO
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
ADO
ADl
AD2
AD3
AD4
AD5
ADS
AD7
VSS
"PO
8085A
Vee
HOLD
HLDA
eLK lOUT)
RESET IN
READY
loiM
Sl
RD
WR
ALE
So
A15
A14
A13
A12
All
AlO
Ag
AS
REV/2
EI
397

1 Page





UPD8085A-2 pdf, ピン配列
p.PD8085A
PIN IDENTI FICATION
PIN
NO. SYMBOL
NAME
FUNCTION
1.2 X" X2
RO
Crystal In
Reset Out
Crystal, RC, or external clock mput
Acknowledge that the processor is being reset to be
used as a system reset
SOD
Serial Out Data
'·blt data out by the SIM Instruction
SID
Senal In Data
1-blt data Into ACe bit 7 by the RIM Instruction
Trap
Trap Interrupt
Input
Highest priority nonmaskable restart Interrupt
RST 7.5
RST 6.5
RST 5.5,
Restart
Interrupts
Priority restart interrupt Inputs, of which 7.5 IS the
highest and 5.5 the lowest priority
10 I INTR
Interrupt
A general Interrupt Input which stops the PC from
Request In
incrementing, generates INTA, and Samples the data
Ir-----~-=~-----+------.---b-us~fo~r ~a r~es~tar~t o~r c~all~In~str~t.i-ctio-n --------­
11 INTA
Interrupt
An output which indicates that the processor has
Acknowledge
responded to INTR
12-19
ADO - AD7
i
20 i VSS
21·28
AS - A1S
low
Address/Data Bus
Ground
High Address Bus
Multiplexed low address and data bus
Ground Reference
Nonmultiplexed high 8·blts of the address bus
29,33
SO, S,
I
30 ALE
Status Outputs
Address Latch
Enable Out
Outputs which indicate data bus status: Halt, Write.
Read, Fetch
A Signal which indicates that the lower 8·blts of
address are valid on the AD lines
31. 32
WR, RD
Write/Read
Strobes Out
Signals out which are used as write and read strobes
for memory and 110 deVices
34 101M
1/0 or Memory
Indicator
A signal out which Indicates whether RD or WR
strobes are for 110 or memory deVices
35 Ready
Ready Input
An input whiCh IS used to rncrease the data and
address bus access times (can be used for slow
memory)
36 Reset In
Reset Input
An Input which IS used to start the processor activity
at address O. resetting IE and HLDA flip-flops
37
38,39
elK
HLDA, HOLD
~Clo~ck ~Out______~~sY~'_te._m_e_'O_'_k~o_u~tp_u_t__________________ ___
Hold Acknowledge
Out and Hold
Input Request
Used to request and Indlcat~ that the processor should
relinquish the bus for OMA activity. When hold IS
acknowledged. RD. WR. 10/M". Address and Data
busses are all 3-st-ated
40 Vee
5V Supply
Power Supply Input
ABSOLUTE MAXIMUM
RATINGS*
Operating Temperature ..
Storage Temperature (Ceramic- Package).
(Plastic Package) , ..
All Output Voltages.
All Input Voltages, .
Supply Voltage Vee.
Power Dissipation ..
o°C to +70°C
-65°e to +150o e
-40oe to +125°e
-0.3 to +7 Volts
-0.3 to +7 Volts
-0.3 to +7 Volts
1.5W
DC CHARACTE RISTICS
COMMENT: Stress above those listed under "Absolute Maximum Ratings' may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated In the operational sections of this speCification IS not
implied. Exposure to absolute maximum rating conditions for extended periods may affect deVice
relIability.
"Ta '" 25°C
T.· o°c to +70°C, Vec' +5V ± 10%, VSS' GND, unless othe,wis. specified
PARAMETER
SYMBOL
MIN
LIMITS
TVP MAX
UNIT
TEST
CONDITIONS
Input Low Voltage
Input High Voltage
Vil VSS - 0.5
V,H 2.0
Output Low Voltage
Output High Voltage
Power Supply Current (V cel
VOL
VOH
Ice (A V)
2,4
Input Leakage
I,l
OUtput Leakage
'lO
Input Low Level. Reset
VILA
-0.5
Input High Level, Reset
VtHR
2,4
Hysteresis. Reset
VHV
0.25
<DNote:
Minus I-I designates current flow out of the device.
VSS + 0.8
V
Vee + 0.5 V
0.45
170
.00 ·CD
"0 CD
V IOL'" 2 mA on all outputs
CDV IOH ;: -400 IJ.S
mA tcy mm
.A V,N • Vee
.A O.45V ..-;: VOUT ..-; Vee
+0.8
V
VCC + 0.5
V
V
399


3Pages


UPD8085A-2 電子部品, 半導体
jLPD8085A
PROCESSOR STATE
TRANSITION DIAGRAM
(READY + BII (j)
READY + BI (j)
SET
HLDA FF
VAll DINT
RESET
HALT FF
seT
HLDA FF
SET
INTA FF
RESET
INTE FF
HOLD
SET
INTA FF
RESET
INTE FF
Notes:
<D BI indicates that the bus is idle during this machine cycle.
® CK indicates the number of clock cycles in this machine cycle.
402

6 Page



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部品番号部品説明メーカ
UPD8085A-2

Single Chip 8-BIT N-CHANNEL MICROPROCESSOR

NEC
NEC


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