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UPD416-2 の電気的特性と機能

UPD416-2のメーカーはNECです、この部品の機能は「16K x 1-Bit DYNAMIC NMOS RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD416-2
部品説明 16K x 1-Bit DYNAMIC NMOS RAM
メーカ NEC
ロゴ NEC ロゴ 




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UPD416-2 Datasheet, UPD416-2 PDF,ピン配置, 機能
NEe Microcomputers, Inc.
18384 x 1 BIT DYNAMIC MOS
RANDOM ACCESS MEMORY
NEe
f' PD416
P. PD416·1
f' PD416·2
f'PD416·3
J.L PD416·5
DESCPIIIPTION
The NECI1PD416 is a 16384 words by 1 bit Dynamic MOS RAM. It is designed for
memory applications where very low cost and large bit storage are important design
objectives.
The I1PD416 .is fabr,icated using a double-poly-layer N channel silicon gate process
which affords high -storage cell density and high performance. The use of dynamic
circuitry throughout, including the sense amplifiers, assures minirnal power dissipation.
II
Multiplexed address inputs permit the IlPD416 to be packaged in the standard 16 pin
dual-in-line package. The 16 pin package provides the highest system bit densities and
is available in either ceramic or plastic. Noncritical clock timing requirements allow
use of the multiplexing technique while maintaining high perforrnance.
F I!:AT U iii ES
16384 Words x 1 Bit Organization
• High Memory Density - 16 Pin Ceramic and Plastic Packages
• Multiplexed Address Inputs
• Standard Power Supplies +12V, - 5V, +5V
• Low Power Dissipation; 462 mW Active (MAX)' 40 mW Standby (MAX)
• Output Data Controlled by CA'S and Unlatched at End of Cycle
• Read-Modify-Write, RAS-only Refresh, and Page Mode Capability
• All Inputs TTL Compatible, and Low Capacitance
• 128 Refresh Cycles
• 5 Perform~nce Ranges:
I1PD416
_- I1PD416-1
.. I1PD416-2
I1PD416-3
I1PD416-5
ACCESS liME
300 ns
250 n$ ~
200 ns
150 ns
120 ns
RIW CYCLE
510 ns
410 ns
375 ns
375 ns
320 ns
RMW CYCLE
575 ns
465 ns
375 ns
375 ns
320 ns
PIN CONFIGURATION
vBB
DIN
WRITE
RAS
AO
A2
Al
VDD
Vss
CAS
DOUT
A6
A3
A4
A5
Vee
AO-A6
CAS
DIN
DOUT
RAS
WRITE
VBe
VCC
VDD
VSS
Address Inputs
Column Address Strobe
Data In
Data Out
Row Address Strobe"
ReadlWrite
Power (-5Vl
Power (+5Vl
Power (+12Vl
Ground
Rev/2
27

1 Page





UPD416-2 pdf, ピン配列
DC CHARACTERISTICS
fL PD416
Ta == O°CtO+70°CQ), VOO= +12V:!: 10%, Vee= +5V ± 10%, Vas =-5V ± 10%, Vss= OV
PARAMETER
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Input High (Logic 1)
Voltage, RAS, CAS,
WRITE
Input High i Logic 1}
Voltage, all inputs
except RAS. CAS
WRITE
Input Low (Logic Ol
Voltage, all inputs
SYMBOL
VOO
VCC
VSS
VSS
VIHC
VIH
VIL
Operating VOO Current
10D1
Standby VOO Current
RefreShl~11 Speeds
VOO except ,u.PD416-5
ICurrent
"P0416-5
10D2
1003
1003
Page Mode VOO
Current
1004
Operating Vee
Current
'CC1
LIMITS
MIN
TYP
10.8 12.0
4.5 5.0
00
- 4.5 -5.0
MAX
13.2
5.5
0
-5.5
UNIT
V
V
V
V
2.7 7.0 V
TEST
CONDITIONS
@
@@
@
@
@
2.4
7.0 V
@
1.0
0.8 V
@
35 rnA
1.5 rnA
RAS, CAS cycling;
®'RC = 'RC Min.
RAS = V'HC. 00UT
co High Impedance
25 rnA RAS cycllng,CAS '"
®V'HC;tRC = 375 ns
21 rnA
RAS = V,L. CAS
27 rnA cycling; tpc '"
225 ns@
RAS. CAS cycling,
I ®"A 'RC " 375 ns
II
Standby Vee Current
Refresh Vee Current
Page Mode Vee
Current
Operating VSB
Current
Standby VSS
Current
'CC2
-10
'CC3
-10
'CC4
ISS1
ISS2
10 "A
- --.-- -----
10 "A
MA
--r--
200 MA
100 MA
RAS= V'HC.
DOUT -0 High
I mpt:;dance
RAS cyclmg,
CAS V,HC·
'RC 375 ns
--
RAS VIL· CAS
225 n~®1
RAS. CAS cycling
IRC 375 ns
RAS VIHC·
Dour HI(Jh
Impedance
Refresh Vas
Current
Page Mode VSS
Current
'SS3
ISS4
RAS cycling,
200 "A I CAs" VIHC,
I IRe = 375 ns
RAS" V,L. CAS
200 "A cycling;
tpc " 225 ns
Input Leakage
(any input)
'IILI -10
VBS = -5V. OV "
VIN.'(+7V,
10 "A all other pins not
under test =: OV
Output Lea kage
'OILi
-10
10 MA DOUT is disabled,
OV l( VOUT ",;; +5.5V
Output High Voltage
ILogic 11
VOH
2.4
V 'OUT = --5 mA@
Output Low Voltage
(Logic 0)
VOL
0.4 V
'OUT = 4.2 mA
CDNotes: T a is specified here for operation at frequencies to IRe::;' IRC (min). Operation at higher cycle rates with reduced
ambient temperatures and high power dissipation is permissible, however. provided AC operating parameters are met.
See Figure 1 for derating curve.
Q) All voltages referenced 10 VSS.
@ Output voltage >MIl swing from VSS to Vee when activated with no current loading. For purposes of maintaining
data in standby mode, Vee may be reduced to VSS without affecting refresh operations or data retention. However,
the VOH (min) specification is not guaranteed If1 this mode.
@) 1001, 1003, and IOD4 depend on cycle rate. See Figures 2, 3 and 4 for 100 limits at other cycle rates
® il~~d~~~~1ff5~~~~~ tU:~~t~~t~t~t~~~~li~;h~rutrii~~sr~~dCO~~~s~s~~g~f \~::~ad;t~u~~e~ti: ~~~y~ected through a low
29


3Pages


UPD416-2 電子部品, 半導体
,.,. PD416
READ CYCLE
~--------------------'RC------------------~
I--------------------'RAS---------.
V 1HC ----~t------
RAS
~------~
V IL _
TIMING WAVEFORMS
CAS
VIHC~
V 1L_·
ADORESSES
V 1H _
V1l_
VIHC_7T.~~~~~~~------~---------------------4---,~~T.M~~
V 1L_
WRITE CYCLE
I.,o------------------'RC ----------------------,
V 1HC_
CAS
ADDRESSES
- - - - - -____________________ O'EN______________________________
READ·WRITE/READ·MODIFY-WRITE CYCLE
~----------------------'RWC------------------------1
ADDRES!iES
O'N
32

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD416-1

16K x 1-Bit DYNAMIC NMOS RAM

NEC
NEC
UPD416-1

16384 x 1 Bit DYNAMIC NMOS RAM

NEC
NEC
UPD416-2

16K x 1-Bit DYNAMIC NMOS RAM

NEC
NEC
UPD416-2

16384 x 1 Bit DYNAMIC NMOS RAM

NEC
NEC


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