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UPD4164-1 の電気的特性と機能

UPD4164-1のメーカーはNECです、この部品の機能は「65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD4164-1
部品説明 65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY
メーカ NEC
ロゴ NEC ロゴ 




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UPD4164-1 Datasheet, UPD4164-1 PDF,ピン配置, 機能
NEe Microcomputers, Inc.
65,536 x 1 BIT DYNAMIC
RANDOM ACCESS MEMORY
NEe
Jo&PD4164-1
,.,. PD4164-2
J.L PD4164-3
~rn~[m~~~illrnw
DESCR IPTI ON
The NEC /lPD4164 is a 65,536 words by 1 bit Dynamic N-Channel MOS RAM designed
to operate from a single +5V power supply. The negative-voltage substrate bias is
internally generated - its operation is both automatic and transparent.
The /lPD4164 utilizes a double-poly-layer N-channel silicon gate process which provides
high storage cell density, high performance and high reliability.
The /lPD4164 uses a single transistor dynamic storage cell and advanced dynamic
circuitry throughout, including the 512 sense amplifiers, which assures that power
dissipation is minimized. Refresh characteristics have been chosen to maximize yield
(low cost to user) while maintaining compatibility between Dynamic RAM generations.
The /lPD4164 three-state output is controlled by CAS, independent of RAS. After a
valid read or read-modify-write cycle, data is held on the output by holding CAS low.
The data out pin is returned to the high impedance state by returning CAS to a high
state. The /lPD4164 hidden refresh feature allows CAS to be held low to maintain
output data while RAS is used to execute RAS only refresh cycles.
Refreshing is accomplished by performing RA"S" only refresh cycles, hidden refresh
cycles, or normal read or write cycles on the 128 address combinations of AO through
A6 during a 2 ms period.
FEATURES
Multiplexed address inputs permit the /lPD4164 to be packaged in the standard 16
pin dual-in-line package. The 16 pin package provides the highest system bit densities
and is compatible with widely available automated handling equipment.
High Memory Density
• MUltiplexed Address Inputs
• Single +5V Supply
• On Chip Substrate Bias Generator
• Access Time: /lPD4164-1 - 250 ns
/lPD4164-2 - 200 ns
/lPD4164-3 - 150 ns
• Read, Write Cycle Time: /lPD4164-1 - 410 ns
/lPD4164-2 - 335 ns
/lPD4164-3 - 270 ns
• Low Power Dissipation: 250 mW (Active); 28 mW (Standby)
• Non-Latched Output is Three-State, TTL Compatible
• Read, Write, Read-Write; Read-Modify-Write, RAS Only Refresh, and Page Mode
Capability
• All Inputs TTL Compatible, and Low Input Capacitance
• 128 Refresh Cycles (AO-A6 Pins for Refresh Address)
• CAS Controlled Output Allows Hidden Refresh
• Available in Both Ceramic and Plastic 16 Pin Packages
PIN CONFIGURATION
NC
DIN
WE
RAS
AO
A2
A1
VCC
VSS
CAS
DOUT
A6
A3
A4
A5
A7
AO-A7
RAS
CAS
WE
DIN
DOUT
VCC
VSS
NC
PIN NAMES
Address Inputs
Row Address Strobe
Col umn Address Strobe
Write Enable
Data Input
Data Output
Power Supply (+5V)
Ground
No Connection
47

1 Page





UPD4164-1 pdf, ピン配列
jLPD4164
AC CHARACTERISTICS
Ta "00 to +70"CG); Vcc - +5V:!: 10%: VSS· OV @ @
PARAMETER
SYMBOL
,dID4184-1
MIN MAX
LIMITS
~184-2
MIN MAX
pP041M-3
MIN MAX
TEST
UNIT CONDITIONS
Random Read or Write
Cycle Time
Read Write Cycle Time
Page Mode Cycle Time
Access Time from RAS
AccltSfi Time from CAs
Output Buffer Turn-Off
Oelay
Transition Time IRiM and
Fall)
RAS Precharge Time
RAS Pulse Width
RAS Hold Time
CAS Pulse Width
CAS Hold Time
RAS to CAS Delay Time
CAS to RAS Precharge Time
CAS Precherge Time
CAS Precharge Time (For
Pa~ Mode C~18 Only)
RAS Pracharge ~Hold
Time
Row Addreu Set-Up Time
Row Address Hold Time
Column Addrs. Set-UP
Time
Column Addl'8Sl Hold Time
Column Addres. Hold Tima
Referenced toRAS
'RC
'RWC
'PC
tRAC
tCAC
tOFF
IT
'RP
tRAS
tRSH
'CAS
tCSH
tRCD
tCRP
tCPN
'CP
'RPC
tASA
tRAH
'ASC
teAH
'AR
410 335 270
46. 335 270
275 225 170
250 200 150
165 135 100
60 50 40
50 50 50
150 120 100
250 10,000 200 10,000 150 10.000
16. 13S 100
16. 10.000 13. 10,000 100 10,000
250 200 150
35 85 30 8S 2. .0
35 30 25
100 80 60
25 20
75 65
160 120
15
4.
95
®
®
®®
®
®
qg
Read Commend Set·Up
Time
'RCS
Read Command Hold Time
tRRH
30
25
20
Referenced toRAS
Rnd Commend Hold Time
tRCH,
0
()
Write Command Hold Time
Write Command Hold Time
Referenced to""fiAS
Write Commend Pul.. Width
Write Command to RAS
LeaclTime
'WCH
-WCR
'WP
tRWL
75
160
75
100
55
.120
55
45
95
45
45
Write Command to CAS
Lead Time
Data·ln Set·Up Time
Date·ln Hold Time
Date-In Hold Time
Referenced to1iAS
'ewL
'OS
'OH
tDHR
100
75
160
65
55
120
45
4S
95
{}
{}
Refr..h Period
WRITE Command Set-Up
Time
CAS to WFii=rr D.I.V
RAS to WRITE Datay
tREF
'wes
'ewo
tRWD
20
116
200
20 -20
80 60
14S '110
\21
~
()
<DNotal:
T.i. spectfled here for operation at frequencies to tRC;;" tRC Iml"l_ Operation at higher cvcle ram with reduced
ambient temperatures end higher power dllllpation Is permiuible, however. provided AC operating perameters are met.
® An Initial p,aUle of 100 ~ Is required after power-up followed by eny 8 Jti:!cvdes before pr0p8r device operation is
achieved.
@ AC measurements auume tT '" 5 ns.
@ VIHC Imin) or VIH (min) and VIL Ime~) are reference IIMIII for 1T118SI.Iring timing of j"put signals, Also, transition
tlmel .... measured between VIHC or VIH end VIL'
(§) ~f~~=i:~!~a~~ :;:~):~~ ~~~~I~n!.::: onlv to Indicate cvcle times at which proper operation owr
@ Allum.. that tRCS < tRCD Imax). If tRCS il greeter then the m.~imum recommended wlue shown in this table.
tRAC wlllincre. . by the amount that tRCo exceedl the wthiltS shown.
(i) Allumes that tRCD > tRCO Ima~).
@ ~Ured with • load aquiWIlWlt to 2 TTlloeds end 100 pF.
@ tOFF (med dtf",.. the tlme.t which the outPUt achlevts the OIJ8n circuit condition and II not ...ferenced to OU1P1It
voItegrlevels.
~ ()pemion within the tRCD (mex) limit enlu.... that tRAC (mIIX) can t. met, tRCO (max) is specifled In a....m.nce
o point onlV, If tACO Is greater then th.speclfled tACO (max) limit, then acoe. time is controllec:lexclualwlv bV tCAt.
TheM perllmetel'l.,. referenced to ~ leadil'll edlll In ..rtV write c:yda. a'\Cf to WJ!fiTE 1_lnl edlll jn dtlayed write
or nted-modlfy-wrlte cyd...
0) twcs. tcWD and tAWO .... muled_ operatl"" perarnet8rs In ...ed-wrlte lAd re.t-modlfy-wri1e cydn only. If twcs;;"
twcs Imlnl. the evcle II en _Iv write cyde end the date output will ..........n open circuit throughout the ..,ti... cyde.
If tcwD;;" tCWD (mil'll If'Id tRWD > tRWD (min). the cycle It • tfled-wrtte and the de.. OUtpu1 will c:onteIn cine rem
from the _!ectad cell. It neither of the above conditio"' .... met the condltJon of 1M data out Cat accHI 14m. Ind until
~goesbeck lOVIH) is Indatannlnate.
4) Etther tARH or tRCH must t. ..dlfled for e Nad cycle.
II
49


3Pages


UPD4164-1 電子部品, 半導体
'J.'PD4164
Ta =O· to +70·C;VCC =+5V ± 10%; VSS =OV
PARAMETER
Input Capacitance
(AO-A7), DIN
Input Capacitance
RAS, CAS, WRITE
Output Capacitan<:e
(DOUT)
SYMBOL
C}1
C}2
Co
LIMITS
MIN TYP MAX
56
10
"
7
UNIT
pF
pF
pF
TEST
CONDITIONS
CAPACITANCE
PACKAGE OUTLINES
IlPD4164C
ITEM
A
L'
M
Plastic
MILLIMETERS
19.4 MAX.
0.81
2."
0.5
11.78
1.3
2.54 MIN.
O.eMIN.
4.06 MAX.
4.56 MAX.
7.62
B.'
+0.10
0.25
-0.06
INCHES
0.76 MAX.
0.03
0.10
0.02
0.10
0.061
O.IOMIN.
-"~
o.lBMAX.
.,1--/-- - A - - - - - i
ITIM
A
C
D
E
F
G
H
I
J
K
M
Ceramic
MILLIMETERS
20.6 MAX.
1.38
.2..."
17.78
1.3
301 MIN•.
D.IMIN.
.... MAX.
1.1 MAX.
7.•
7.3
0.37
INCHIS
0.81 MAX.
0.0.
0.'0
0.02
0.70
0.01'
0.14 MIN.
0:02 MIN.
0.11MA)(,
o.ZOMAK.
0.30
0.21
0.01.
52
IlPD4164D
0-lo"~ r-
4164DS.g.gO-CAT

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UPD4164-1

65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY

NEC
NEC
UPD4164-2

65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY

NEC
NEC
UPD4164-3

65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY

NEC
NEC


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