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TC58DVM92A5TAI0 の電気的特性と機能

TC58DVM92A5TAI0のメーカーはToshibaです、この部品の機能は「512M-BIT (64M x 8 BITS) CMOS NAND E2PROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 TC58DVM92A5TAI0
部品説明 512M-BIT (64M x 8 BITS) CMOS NAND E2PROM
メーカ Toshiba
ロゴ Toshiba ロゴ 




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TC58DVM92A5TAI0 Datasheet, TC58DVM92A5TAI0 PDF,ピン配置, 機能
TC58DVM92A5TAI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
512-MBIT (64M × 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The device is a single 3.3 V 512Mbit (553,648,128 bit) NAND Electrically Erasable and Programmable Read-Only
Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 4096 blocks. The device has a 528-byte static
register which allows program and read data to be transferred between the register and the memory cell array in
528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes ×
32 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell allay 528 × 128K × 8
Register
528 × 8
Page size
528 bytes
Block size
(16K + 512) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
Mode control
Serial input/output
Command control
Power supply
VCC = 2.7 V to 3.6 V
Access time
Cell array to register 25 μs max
Serial Read Cycle 40 ns min
Program/Erase time
Auto Page Program 300 μs/page typ.
Auto Block Erase 2.5 ms/block typ.
Operating current
Read (40 ns cycle)
Program (avg.)
Erase (avg.)
Standby
20 mA max.
20 mA max.
20 mA max.
50 μA max
Package
TSOPI48-P-1220-0.50 (Weight: 0.53g typ.)
1 2010-07-13

1 Page





TC58DVM92A5TAI0 pdf, ピン配列
BLOCK DIAGRAM
I/O1
to
I/O8
CE
CLE
ALE
WE
RE
WP
RY/BY
I/O Control circuit
Logic control
RY/BY
Status register
Address register
Command register
Control
HV generator
TC58DVM92A5TAI0
VCC VSS
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VCC
VIN
VI/O
PD
Tsolder
Tstg
Topr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
VALUE
0.6 to 4.6
0.6 to 4.6
0.6 V to VCC + 0.3 V (4.6 V)
0.3
260
55 to 125
-40 to 85
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
CIN Input
VIN = 0 V
COUT
Output
VOUT = 0 V
* This parameter is periodically sampled and is not tested for every device.
MIN
MAX
10
10
UNIT
V
V
V
W
°C
°C
°C
UNIT
pF
pF
3 2010-07-13


3Pages


TC58DVM92A5TAI0 電子部品, 半導体
TC58DVM92A5TAI0
Note:
(1) CE High to Ready time depends on the pull-up resister tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30
ns , RY / BY signal stays Ready.
tCEH 100 ns
* *: VIH or VIL
CE
RE
RY/BY
525
AC TEST CONDITIONS
PARAMETER
Vcc
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
527 A
A : 0 to 30 ns Busy signal is not output.
Busy
tCRY
CONDITION
2.7V to 3.6V
VCC 0.2 V, 0.2 V
3 ns
VCC / 2
VCC / 2
CL (100 pF) + 1 TTL
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = -40° to 85°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
tPROG
Programming Time
N
Number of Programming Cycles on Same
Page
tBERASE
Block Erasing Time
(1): Refer to Application Note (12) toward the end of this document.
TYP.
300
2.5
MAX
700
3
7
UNIT
μs
ms
NOTES
(1)
6 2010-07-13

6 Page



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部品番号部品説明メーカ
TC58DVM92A5TAI0

512M-BIT (64M x 8 BITS) CMOS NAND E2PROM

Toshiba
Toshiba


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