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PDF UT61256C Data sheet ( Hoja de datos )
| Número de pieza | UT61256C | |
| Descripción | 32K x 8 BIT HIGH SPEED CMOS SRAM | |
| Fabricantes | UTRON | |
| Logotipo |  |
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UTRON
Rev. 1.2
FEATURES
Fast access time : 8/10/12/15 ns (max.)
Low operating power consumption :
80 mA (typical)
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 28-pin 300 mil SOJ
28-pin 8mm×13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
A0-A14
Vcc
Vss
DECODER
32K × 8
MEMORY
ARRAY
I/O1-I/O8
I/O DATA
CIRCUIT
COLUMN I/O
CE
OE
CONTROL
CIRCUIT
WE
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
UT61256C
32K X 8 BIT HIGH SPEED CMOS SRAM
The UT61256C is a 262,144-bit high-speed
CMOS static random access memory organized
as 32,768 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT61256C is designed for high-speed
system applications. It is particularly suited for
use in high-density high-speed system
applications.
The UT61256C operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
SOJ
OE 1
A11 2
28
27
A9 3
26
A8 4
25
A13 5
WE 6
24
23
Vcc 7
22
A14 8 UT61256C 21
A12 9
A7 10
A6 11
20
19
18
A5 12
17
A4 13
16
A3 14
15
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
STSOP
GENERAL DESCRIPTION
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
P80031
1 page  
UTRON
Rev. 1.2
UT61256C
32K X 8 BIT HIGH SPEED CMOS SRAM
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6)
Address
t WC
CE
WE
t AS
t AW
t CW
t WP
t WR
Dout
Din
t WHZ
(4)
High-Z
t DW
t OW
t DH
Data Valid
(4)
WRITE CYCLE 2 ( CE Controlled) (1,2,5)
Address
t WC
CE t AS
t AW
t CW
t WR
WE t WP
Dout
t WHZ
High-Z
t DW
t DH
Din
Data Valid
Notes :
1. WE and CE must be HIGH during all address transitions.
2. A write occurs during the overlap of a low CE and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off
and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the CE low transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state.
6. tOW and tWHZ are specified with CL = 5pF. Transition is measured ± 500mV from steady state.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
P80031
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UT61256C.PDF ] | |
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