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PDF CD4538BM Data sheet ( Hoja de datos )
| Número de pieza | CD4538BM | |
| Descripción | Dual Precision Monostable | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 1988
CD4538BM CD4538BC Dual Precision Monostable
General Description
The CD4538B is a dual precision monostable multivibrator
with independent trigger and reset controls The device is
retriggerable and resettable and the control inputs are inter-
nally latched Two trigger inputs are provided to allow either
rising or falling edge triggering The reset inputs are active
low and prevent triggering while active Precise control of
output pulse-width has been achieved using linear CMOS
techniques The pulse duration and accuracy are deter-
mined by external components RX and CX The device does
not allow the timing capacitor to discharge through the tim-
ing pin on power-down condition For this reason no exter-
nal protection resistor is required in series with the timing
pin Input protection from static discharge is provided on all
pins
Features
Y Wide supply voltage range
3 0V to 15V
Y High noise immunity
Y Low power
TTL compatibility
0 45 VCC (typ )
Fan out of 2 driving 74L
or 1 driving 74LS
Y New formula PWOUT e RC
(PW in seconds R in Ohms C in Farads)
Y g1 0% pulse-width variation from part to part (typ )
Y Wide pulse-width range
1 ms to %
Y Separate latched reset inputs
Y Symmetrical output sink and source capability
Y Low standby current
Y Pin compatible to CD4528B
5 nA (typ )
5 VDC
Block and Connection Diagrams
Dual-In-Line Package
CD4538BM
CD4538BC
Top View
Order Number CD4538B
RX and CX are External Components
VDD e Pin 16
VSS e Pin 8
Truth Table
TL F 6000 – 1
Inputs
Clear A
LX
XH
XX
HL
Hu
B
X
X
L
v
H
Outputs
QQ
LH
LH
LH
H e High Level
L e Low Level
u e Transition from Low to High
v e Transition from High to Low
e One High Level Pulse
e One Low Level Pulse
X e Irrelevant
TL F 6000 – 2
C1995 National Semiconductor Corporation TL F 6000
RRD-B30M105 Printed in U S A
1 page  
Theory of Operation
FIGURE 2
TL F 6000 – 4
Trigger Operation
The block diagram of the CD4538B is shown in Figure 1
with circuit operation following
As shown in Figures 1 and 2 before an input trigger occurs
the monostable is in the quiescent state with the Q output
low and the timing capacitor CX completely charged to
VDD When the trigger input A goes from VSS to VDD (while
inputs B and CD are held to VDD) a valid trigger is recog-
nized which turns on comparator C1 and N-Channel tran-
sistor N1 j At the same time the output latch is set With
transistor N1 on the capacitor CX rapidly discharges toward
VSS until VREF1 is reached At this point the output of com-
parator C1 changes state and transistor N1 turns off Com-
parator C1 then turns off while at the same time comparator
C2 turns on With transistor N1 off the capacitor CX begins
to charge through the timing resistor RX toward VDD When
the voltage across CX equals VREF2 comparator C2 chang-
es state causing the output latch to reset (Q goes low) while
at the same time disabling comparator C2 This ends the
timing cycle with the monostable in the quiescent state
waiting for the next trigger
A valid trigger is also recognized when trigger input B goes
from VDD to VSS (while input A is at VSS and input CD is at
VDD) k
It should be noted that in the quiescent state CX is fully
charged to VDD causing the current through resistor RX to
be zero Both comparators are ‘‘off’’ with the total device
current due only to reverse junction leakages An added
feature of the CD4538B is that the output latch is set
via the input trigger without regard to the capacitor voltage
Thus propagation delay from trigger to Q is independent of
the value of CX RX or the duty cycle of the input waveform
Retrigger Operation
The CD4538B is retriggered if a valid trigger occurs l fol-
lowed by another valid triggerm before the Q output has
returned to the quiescent (zero) state Any retrigger after
the timing node voltage at pin 2 or 14 has begun to rise from
VREF1 but has not yet reached VREF2 will cause an in-
crease in output pulse width T When a valid retrigger is
initiated m the voltage at T2 will again drop to VREF1 before
progressing along the RC charging curve toward VDD The
Q output will remain high until time T after the last valid
retrigger
Reset Operation
The CD4538B may be reset during the generation of the
output pulse In the reset mode of operation an input pulse
on CD sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor Q1 n When
the voltage on the capacitor reaches VREF2 the reset latch
will clear and then be ready to accept another pulse If the
CD input is held low any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change Since the Q output is reset when an input low level
is detected on the CD input the output pulse T can be made
significantly shorter than the minimum pulse width specifica-
tion
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CD4538BM.PDF ] | |
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