DataSheet.jp

CD4538BC の電気的特性と機能

CD4538BCのメーカーはFairchild Semiconductorです、この部品の機能は「Dual Precision Monostable」です。


製品の詳細 ( Datasheet PDF )

部品番号 CD4538BC
部品説明 Dual Precision Monostable
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




このページの下部にプレビューとCD4538BCダウンロード(pdfファイル)リンクがあります。

Total 11 pages

No Preview Available !

CD4538BC Datasheet, CD4538BC PDF,ピン配置, 機能
October 1987
Revised January 1999
CD4538BC
Dual Precision Monostable
General Description
The CD4538BC is a dual, precision monostable multivibra-
tor with independent trigger and reset controls. The device
is retriggerable and resettable, and the control inputs are
internally latched. Two trigger inputs are provided to allow
either rising or falling edge triggering. The reset inputs are
active LOW and prevent triggering while active. Precise
control of output pulse-width has been achieved using lin-
ear CMOS techniques. The pulse duration and accuracy
are determined by external components RX and CX. The
device does not allow the timing capacitor to discharge
through the timing pin on power-down condition. For this
reason, no external protection resistor is required in series
with the timing pin. Input protection from static discharge is
provided on all pins.
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VCC (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
s New formula: PWOUT = RC (PW in seconds, R in Ohms,
C in Farads)
s ±1.0% pulse-width variation from part to part (typ.)
s Wide pulse-width range: 1 µs to
s Separate latched reset inputs
s Symmetrical output sink and source capability
s Low standby current: 5 nA (typ.) @ 5 VDC
s Pin compatible to CD4528BC
Ordering Code:
Order Number Package Number
Package Description
CD4538BCM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4538BCWM
M16B
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
CD4538BCN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP and SOIC
Top View
Inputs
Outputs
Clear A B Q Q
L XXLH
X HXLH
X XLLH
H L
H H
H = HIGH Level
L = LOW Level
↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW
= One HIGH Level Pulse
= One LOW Level Pulse
X = Irrelevant
© 1999 Fairchild Semiconductor Corporation DS006000.prf
www.fairchildsemi.com

1 Page





CD4538BC pdf, ピン配列
Theory of Operation
FIGURE 2.
Trigger Operation
The block diagram of the CD4538BC is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and Figure 2, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
to VDD. When the trigger input A goes from VSS to VDD
(while inputs B and CD are held to VDD) a valid trigger is
recognized, which turns on comparator C1 and N-Channel
transistor N1(1). At the same time the output latch is set.
With transistor N1 on, the capacitor CX rapidly discharges
toward VSS until VREF1 is reached. At this point the output
of comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time com-
parator C2 turns on. With transistor N1 off, the capacitor CX
begins to charge through the timing resistor, RX, toward
VDD. When the voltage across CX equals VREF2, compara-
tor C2 changes state causing the output latch to reset (Q
goes low) while at the same time disabling comparator C2.
This ends the timing cycle with the monostable in the qui-
escent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goes
from VDD to VSS (while input A is at VSS and input CD is at
VDD)(2).
It should be noted that in the quiescent state CX is fully
charged to VDD, causing the current through resistor RX to
be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the CD4538BC is that the output latch is set via
the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of CX, RX, or the duty cycle of the input wave-
form.
Retrigger Operation
The CD4538BC is retriggered if a valid trigger occurs(3) fol-
lowed by another valid trigger(4) before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at pin 2 or 14 has begun to rise
from VREF1, but has not yet reached VREF2, will cause an
increase in output pulse width T. When a valid retrigger is
initiated(4), the voltage at T2 will again drop to VREF1 before
progressing along the RC charging curve toward VDD. The
Q output will remain high until time T, after the last valid
retrigger.
Reset Operation
The CD4538BC may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on CD sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor Q1(5). When
the voltage on the capacitor reaches VREF2, the reset latch
will clear and then be ready to accept another pulse. If the
CD input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the CD input, the output pulse T can be
made significantly shorter than the minimum pulse width
specification.
3 www.fairchildsemi.com


3Pages


CD4538BC 電子部品, 半導体
AC Electrical Characteristics (Note 4)
TA = 25°C, CL = 50 pF, and tr = tf = 20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tTLH, tTHL
Output Transition Time
tPLH, tPHL
Propagation Delay Time
VDD = 5V
VDD = 10V
VDD = 15V
Trigger Operation—
A or B to Q or Q
VDD = 5V
VDD = 10V
VDD = 15V
Reset Operation—
100 200
50 100
40 80
ns
ns
ns
300 600
150 300
100 220
ns
ns
ns
tWL, tWH
tRR
CIN
Minimum Input Pulse Width
A, B, or CD
Minimum Retrigger Time
Input Capacitance
CD to Q or Q
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Pin 2 or 14
Other Inputs
250 500
125 250
95 190
35 70
30 60
25 50
0
00
0
10
5 7.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PWOUT
Output Pulse Width (Q or Q)
(Note: For Typical Distribution,
see Figure 6)
Pulse Width Match between
Circuits in the Same Package
CX = 0.1 µF, RX = 100 k
Operating Conditions
RX = 100 k
CX = 0.002 µF
RX = 100 k
CX = 0.1 µF
RX = 100 k
CX = 10.0 µF
RX = 100 k
CX = 0.1 µF
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
208
211
216
8.83
9.02
9.20
0.87
0.89
0.91
226
230
235
9.60
9.80
10.00
0.95
0.97
0.99
±1
±1
±1
244
248
254
10.37
10.59
10.80
1.03
1.05
1.07
µs
µs
µs
ms
ms
ms
s
s
s
%
%
%
RX External Timing Resistance
CX External Timing Capacitance
Note 4: AC parameters are guaranteed by DC correlated testing.
5.0
(Note 5)
k
0 No Limit pF
Note 5: The maximum usable resistance RX is a function of the leakage of the Capacitor CX, leakage of the CD4538BC, and leakage due to board layout,
surface resistance, etc.
www.fairchildsemi.com
6

6 Page



ページ 合計 : 11 ページ
 
PDF
ダウンロード
[ CD4538BC データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
CD4538B

CMOS Dual Precision Monostable Multivibrator

RCA
RCA
CD4538BC

Dual Precision Monostable

Fairchild Semiconductor
Fairchild Semiconductor
CD4538BC

Dual Precision Monostable

National Semiconductor
National Semiconductor
CD4538BM

Dual Precision Monostable

National Semiconductor
National Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap