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PDF UM6114 Data sheet ( Hoja de datos )
| Número de pieza | UM6114 | |
| Descripción | 1K x 4 CMOS SRAM | |
| Fabricantes | UMC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UM6114 (archivo pdf) en la parte inferior de esta página. Total 5 Páginas | ||
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<l)UMC
UM6114
Features
• High speed-45/55/70/90 ns (max.)
• Low power dissipation:
50mW (Typ.) operating
5/NV (Typ.) standby
• Single 5V power supply
• Fully static operation
• All inputs and outputs directly TTL compatible
• Three state outputs
• Data retention supply voltage: 2.0-5.5V
General Description
The UM6114 is a 4,096 bit high speed and low power static
random access memory organized as 1,024 words by 4 bits
using CMOS technology, and operates from a single 5-volt
supply.
The UM6114 is compatible with the industry produced
NMOS 2148 type 4K RAM, yet offers a more than 90%
reduction in power of their NMOS equivalents.
The UM6114 is a fully CMOS RAM, therefore it is suited
for use in low power applications where battery operation
and battery back up for nonvolatility are required.
The UM6114 is guaranteed for data retention at a power
supply as low as 2 volts. The UM6114 is directly TTL
compatible in all inputs and outputs.
The UM6114 is offered in both standard 18 pin plastic and
cerdip packages, 0.3 inches in width.
Pin Configuration
Vee
A7
As
A9
1/01
1/0 2
1/0 3
1/°4
R/W
Block Diagram
A4
As
A6
A7
As
A9
ROW
SELECT
MEMORY ARRAY
64 ROWS
64 COLUMNS
_vcc
_VSS
1/01
1/02
1/03
1/04
COLUMNI/OCI RCU ITS
TROL
CE ----+-a,""'\
Riw -~---ILJ
2-28
1 page  
(l)UMC
WRITE CYCLE 2(1)
ADDRESS
RiW
UM6114
Notes:
1. RlW must be high during all address transitions.
2. A write occurs during the overlap (tWP) of a low CE and a low R/W.
3. tWR is measured form the earlier of EE or R/W going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied.
5. If the CE low transition occures simultaneously with the R/W low transitions or after the R/W transition, outputs remain in a high im-
pedance state.
7. Dout is the same phase of write data of this write cycle.
8. Dout is the read data of next address.
9. If CE is low during this period, I/O pins are in the output state. Then the data input sigQals of opposite phase to the outputs must not be
applied to them.
\
10. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Data Retention Characteristics over the operating temperature range
Symbol
VDR
ICCDR
teDR
tR
Parameter
VCC for Retention Data
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Test Conditions
CE = Vcc
VIN = OV or Vce
Vee = 2.0V, CE = Vee
VIN = OV or Vee
1. Vee =2V, TA =+25°C
2. IRe = Read Cycle Time
Min.
2.0
-
0
tRe(2)
Typ. (1)
-
2
-
-
Max.
-
20
-
-
Units
V
p.A
ns
ns
Timing Waveform Low Vee Data Retention Waveform
VCC ------------------,1
Data Retention Mode
VDR ~2V
eE
Ordering Information
Part Number
Access Time
(Max.)
UM6114
UM6114-1
UM6114-2
UM6114-3
90 ns
70 ns
55 ns
45 ns
UM6114J
UM6114J-1
UM6114J-2
UM6114J-3
90 ns
70 ns
55 ns
45 ns
Operating Current
(Max.)
30mA
30mA
30mA
40mA
30mA
30mA
30mA
40mA
Standby Current
(Max.)
10mA
10 mA
10mA
10mA
10mA
10mA
10mA
10mA
Package Type
Plastic
Plastic
Plastic
Plastic
CERDIP
CERDIP
CERDIP
CERDIP
2-32
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet UM6114.PDF ] | |
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