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UM2364 の電気的特性と機能

UM2364のメーカーはUMCです、この部品の機能は「8K x 8 NMOS ROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 UM2364
部品説明 8K x 8 NMOS ROM
メーカ UMC
ロゴ UMC ロゴ 




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UM2364 Datasheet, UM2364 PDF,ピン配置, 機能
eUMC
UM2364/UM2364A
Features
• 8192 x 8 Bit organization
• Single +5 Volt Supply
• Access Time - 200/300/450 ns (max.)
• Totally static operation
• Completely TT L compatible
• 24 Pin JEDEC approved pinout
General Description
The UM2364 and UM2364A high performance Read Only
Memories are organ ized 8192 words by 8 bits with access
times from 200 ns to 450 ns. The ROMs are designed to
be compatible with all microprocessor and similar applica-
tions where high performance, large bit storage and simple
interfacing are important design considerations. Both
ROMs conform to the JEDEC approved pinout for 24 pin
64K ROMs.
The UM2364 offers the simplest operation (no power
down.) Its programmable chip select allows two 64K
ROMs to be OR-tied without external decoding.
• UM2364A - Automatic power down (CE)
• UM2364 - non power down version
- programmable chip select (CS)
• Three state outputs for wire-OR expansion
• EPROMs accepted as program data input
• 2564 EPROM compatible
The UM2364A offers an automatic power down feature.
Power down is controlled by the Chip Enable (CE) input.
When CE goes high, the device will automatically power
down and remain in a low power standby mode as long as
CE remains high. This unique feature provides system level
power savings as much as 90%.
Both the UM2364 and UM2364A are pin compatible with
the 2564 EPROM thus eliminating the need to redesign
printed circuit boards for volume mask programmed ROMs
after prototyping with EPROMs.
Pin Configuration
Block Diagram
A7
A6
A5
A4
A3
A2
Al
Ao
01
02
03
GND
Vee A7
As A6
A9 As
A12 A4
es A3
AlO A2
All Al
Os Ao
07 01
06 02
Os 03
04 GND
65.536 BIT
ROM ARRAY
(256 x 256)
0,
'-:-1>---0,
0,
'----:--1 :::~--'-- d.
'-------'--'--.. ~.-!-- Os
'-----;-1>--:-:-- d.
'-----~_i·~~07
'------,:>-----'---0,
• CHIP SELECT iCSI IS PROGRAMMABLE LOW ACTIVE, HIGH ACTIVE
OR DONT CARE.
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UM2364 pdf, ピン配列
(l)UMC
Timing Diagrams
Propagation Delay from Address (CE LOW or CS = Active)
A~~~~~~ t-----....
::::j,'AA VAUD ADD""S
D~0~
PREVIOUS DATA
~
VALID DATA
UM2364 / UM2364A
Propagation Delay from Chip Enable, Chip Select (Address Valid)
_ _ _ _ I 4 - - - - - - - - - t A C E [4]- - - - - - - - . 1
1 4 - - - - - - tACS
CS VALID
,...,....,....,.-,10---+---------_+-__ __________________~~~A
~
[5]
14---- tLZ
-----i~
~~~~~
[5]
tLZ -------i~
VCCCURRENT _ _ _ _+-_______JI 50%
IS6
' - - - - tpD
A.C. Testing Input, Output Waveform
> <2AV
20V
20V
TEST POINTS
OAV
O.BV
INPUT
O.BV
OUTPUT
AC TESTING: INPUTS ARE DRIVEN AT 2AV FOR A LOGIC
"1" AND OAV FOR A LOGIC "a". TIMING MEASUREMENTS
ARE MADE AT 2.0V FOR A LOGIC "1" AND O.BV FOR A
LOGIC "0". INPUT PULSE RISE AND FALL TIMES ARE 5 ns.
A.C. Testing Load Circuit
~~::OUDOUT
775U
100pf (INCLUDING SCOPE AND JIG)
Figure 1.
Programming Instructions
All UMC Read Only Memories (ROM) utilize computer
asided techniques to manufacture and test custom bit
patterns. The customer's bit pattern and address informa-
tion can be supplied to UMC in a number of different ways.
UMC can process customer inputs in EPROM, ROM,
PROM, paper tape, and computer punched cards. Contact
your UMC sales representative for complete details on
each of the various data input formats.
Programming instructions are listed at the end of the
Memory Section.
Package Availability
Ordering Information
Order
Number
UM2364
UM2364-1
UM2364-2
UM2364A
UM2364A-l
UM2364A-2
Access
Time
450 ns
300 ns
200 ns
450 ns
300 ns
200 ns
Operating Standby Package
Current cU'rrent Type
100mA
100mA!
100mA
100mA
100mA
100mA
N.A.*
N.A.
N.A.
12mA
12mA
12mA
Plastic
Plastic
Plastic
Plastic
Plastic
Plastic
* Not Applicable.
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共有リンク

Link :


部品番号部品説明メーカ
UM2364

8K x 8 NMOS ROM

UMC
UMC
UM2364A

8K x 8 NMOS ROM

UMC
UMC
UM2366

8K x 8 NMOS ROM

UMC
UMC
UM2366A

8K x 8 NMOS ROM

UMC
UMC


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