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RTL8139BL の電気的特性と機能

RTL8139BLのメーカーはRealtek Microelectronicsです、この部品の機能は「SINGLE CHIP FAST ETHERNET CONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 RTL8139BL
部品説明 SINGLE CHIP FAST ETHERNET CONTROLLER
メーカ Realtek Microelectronics
ロゴ Realtek Microelectronics ロゴ 




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RTL8139BL Datasheet, RTL8139BL PDF,ピン配置, 機能
RTL8139B(L) Preliminary
REALTEK SINGLE CHIP
FAST ETHERNET CONTROLLER
WITH POWER MANAGEMENT
RTL8139B(L)
1. Features:
l 128 pins QFP/LQFP
l Integrated Fast Ethernet MAC, Physical chip
and transceiver in one chip
l 10 Mb/s and 100 Mb/s operation
l Supports 10 Mb/s and 100 Mb/s N-way Auto-
negotiation operation
l PCI local bus single-chip Fast Ethernet
controller
² Compliant to PCI Revision 2.2
² Supports PCI clock 16.75MHz-40MHz
² Supports PCI target fast back-to-back
transaction
² Provides PCI bus master data transfers
and PCI memory space or I/O space
mapped data transfers of RTL8139B(L)'s
operational registers
² Supports PCI VPD (Vital Product Data)
² Supports ACPI, PCI power management
² The RTL8139BL works in 3.3V
signaling environment mainly, and the
RTL8139B is used in 5V signaling
environment only. Both need 5-volt
working voltage as power source.
l Supports CardBus. The CIS can be stored in
93C56 or expansion ROM
l Supports up to 128K bytes Boot ROM
interface for both EPROM and Flash memory
l Supports 25MHz crystal or 50MHz OSC as
the internal clock source. The frequency
deviation of either crystal or OSC must be
within 50 PPM.
l Supports Wake-On-LAN function and remote
wake-up (Magic Packet*, LinkChg and
Microsoft® wake-up frame)
l Supports 4 Wake-On-LAN (WOL) signals
(active high, active low, positive pulse, and
negative pulse)
l Supports auxiliary power-on internal reset, to
be ready for remote wake-up when main
power still remains off
l Supports auxiliary power auto-detect, and sets
the related capability of power management
1999/7/26
1
Rev.2.4

1 Page





RTL8139BL pdf, ピン配列
2. General Description
RTL8139B(L) Preliminary
The Realtek RTL8139B(L) is a highly integrated and cost-effective single-chip Fast Ethernet controller
that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u
100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also supports Advanced
Configuration Power management Interface (ACPI), PCI power management for modern operating
systems that is capable of Operating System Directed Power Management (OSPM) to achieve the most
efficient power management. The RTL8139BL is suitable for the applications of CardBus or mobile with
built-in network controller. The CIS data can be stored in either 93C56 EEPROM or expansion ROM. The
RTL8139B is suitable for 5V signaling environment only, such as modern Desktop environment.
Besides the ACPI feature, the RTL8139B(L) also supports remote wake-up (including Magic Packet*,
LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments. Especially, the
RTL8139B(L) is capable of performing internal reset whenever there is (auxiliary) power applied to. Once
the auxiliary power is on whereas the main power still remains off, the RTL8139B(L) is ready and is
waiting for the Magic Packet* or LinkChnage to wake the system up. Also, the LWAKE pin provides 4
different output signals including active high, active low, positive pulse, and negative pulse. The versatility
of the RTL8139B(L) LWAKE pin satisfies all kinds of motherboards with Wake-On-LAN (WOL)
function. The RTL8139B(L) also supports Analog Auto-Powerdown, that is, the analog part of the
RTL8139B(L) can be shut down temporarily according to the user’s requirement or when the
RTL8139B(L) is in power down states with the wakeup function disabled. Besides, when the analog part
is shut down and the IsolateB pin is low (i.e. the main power is off), then both the analog and digital parts
stop functioning and the RTL8139B(L) will achieve the most power saving and consume extremely minor
power. The rev.F and successors of RTL8139B(L) also support aux. power auto-detect function, and will
auto-configure related bits of their own PCI power management registers in PCI configuration space.
The PCI Vital Product Data (VPD) is also supported to provide the information that uniquely identifies
hardware (i.e., the RTL8139B(L) net card). The information may consist of part number, serial number,
and other detailed information, and so on.
1999/7/26
3
Rev.2.4


3Pages


RTL8139BL 電子部品, 半導体
RTL8139B(L) Preliminary
4. Pin Descriptions
4.1 Power Management/Isolation INTERFACE
Symbol
PMEB
(PME#)
ISOLATEB
(ISOLATE#)
Type
O/D
I
LWAKE/
CSTSCHG
O
Pin No
76
95
83
Description
Power Management Event: Open drain, active low. Used by the
RTL8139B(L) to request a change in its current power management
state and/or to indicate that a power management event has occurred.
Isolate pin: Active low. Used to isolate RTL8139B(L) from the PCI
bus. The RTL8139B(L) does not drive its PCI outputs (excluding
PME#) and does not sample its PCI input (including RST# and
PCICLK) as long as Isolate pin is asserted.
LAN WAKE-UP signal (When CardB_En=0, bit2 Config3): This
signal is used to inform motherboard to execute wake-up process. The
motherboard must support Wake-On-LAN (WOL). There are 4
choices of output, including active high, active low, positive pulse, and
negative pulse, that may be asserted from the LWAKE pin. Please
refer to LWACT bit in CONFIG1 register and LWPTN bit in
CONFIG4 register for the setting of this output signal. The default
output is an active high signal. Once there is a PME event having
come in, the LWAKE and PMEB assert at the same time when the
LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the
LWAKE asserts only when the PMEB asserts and the ISOLATEB is
low.
CSTSCHG signal (When CardB_En=1, bit2 Config3): This signal is
used in CardBus application only and is used to inform motherboard to
execute wake-up process whenever there is PME event occurs. This is
always an active high signal, the setting of LWACT (bit 4, Config1),
LWPTN (bit2, Config4), and LWPME (bit4, Config4) means nothing
in this case.
This pin is a 3.3V signaling output pin.
4.2 PCI INTERFACE
Symbol
AD31-0
C/BE3-0
CLK
CLKRUNB
DEVSELB
Type
T/S
T/S
I
I/O
S/T/S
Pin No
Description
120-123, 125-128, 4-6, PCI address and data multiplexed pins.
8-11, 13, 26-29, 31-34,
37-39, 41-45
2, 14, 24, 36
PCI bus command and byte enables multiplexed pins.
116 Clock provides timing for all transactions on PCI and is input to PCI
device.
75 Clock Run: This signal is used by RTL8139B(L) to request starting (or
speeding up) the clock, CLK. CLKRUNB also indicates the clock
status. For RTL8139B(L), CLKRUNB is an open drain output and also
an input. The RTL8139B(L) requests the central resource to start,
speed up, or maintain the interface clock by the assertion of
CLKRUNB. For the host system, it is an S/T/S signal. The host system
(central resource) is responsible for maintaining CLKRUNB asserted,
and for driving it high to the negated (deasserted) state.
19 Device Select: The RTL8139B(L) asserts this signal low when it
recognizes its target address after FRAMEB is asserted. As a bus
1999/7/26
6
Rev.2.4

6 Page



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部品番号部品説明メーカ
RTL8139B

SINGLE CHIP FAST ETHERNET CONTROLLER

Realtek Microelectronics
Realtek Microelectronics
RTL8139BL

SINGLE CHIP FAST ETHERNET CONTROLLER

Realtek Microelectronics
Realtek Microelectronics


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