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PDF H27UDG8VEM Data sheet ( Hoja de datos )

Número de pieza H27UDG8VEM
Descripción 128 Gb NAND Flash
Fabricantes Hynix 
Logotipo Hynix Logotipo



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No Preview Available ! H27UDG8VEM Hoja de datos, Descripción, Manual

1
Preliminary
H27UDG8VEM Series
128 Gbit (16Gx 8 bit) NAND Flash
128 Gb NAND Flash
H27UDG8VEM
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.2 / APR. 2009
1

1 page




H27UDG8VEM pdf
1
Preliminary
H27UDG8VEM Series
128Gbit (16G x 8 bit) NAND Flash
CE
WE
RE
ALE
CLE
WP
VCC VCCQ
VSS VSSQ
IO0~IO7
R/B
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
VCCQ
VCC
VSSQ
VSS
NC
Data Input / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
I/O Power
Power Supply
I/O Ground
Ground
No Connection
Figure 1 : Logic Diagram
Table 1 : Signal Name
Rev 0.2 /APR. 2009
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H27UDG8VEM arduino
3. DEVICE OPERATION
1
Preliminary
H27UDG8VEM Series
128Gbit (16G x 8 bit) NAND Flash
3.1 Page Read
Upon initial device power up, the device defaults to page read mode. This operation is also initialized by 00 h to the
command register along with followed by five address input cycles. In consecutive read operations, 00h command does
not need to be written for the followed page read operation.
Two types of operations are available: random read, serial page read. The random read mode is enabled when the page
address is changed. The 4,320 bytes of data within the selected page are transferred to the data registers in less than 60us
(tR). The system controller may detect the completion of this data transfer 60us (tR) by analyzing the output of R/B pin.
Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing
RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column
address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output
command. The column address of next data, which is going to be out, may be changed to the address which follows ran-
dom data output command. Random data output can be operated multiple times regardless of how many times it is done
in a page.
3.2 Multi Plane Read
Multi-Plane Page Read is an extension of Page Read, for a single plane with 4,320 byte page registers. Since the device
is equipped with two memory planes, activating the two sets of 4,320 byte page resisters enables a random read of two
pages. Multi-Plane Page Read is initiated by repeating command 60h followed by three address cycles twice. The page and
block addresses for both planes must be identical.
After Read Confirm command (30h) the 8,640 bytes of data within the selected two pages are transferred to the data
registers in less than 60us (tR). The system controller can detect the completion of data transfer (tR) by monitoring the
output of R/B pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h
with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be
read out using the identical command sequences. The restrictions for Multi-Plane Page Read are shown in Figure 13. Multi-
Plane Page Read must be used in the block which has been programmed with Multi-Plane Page Program.
3.3 Page Program
The device is programmed by page. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed 1 times. The addressing should be done in sequential order
in a block. A page program cycle consists of a serial data loading period in which up to 4,320bytes of data may be loaded
into the data register, followed by a non-volatile programming period where the loaded data is programmed into the ap-
propriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the
five cycle address inputs and then serial data. The words other than those to be programmed do not need to be loaded.
The device supports random data input in a page. The column address of next data, which will be entered, may be changed
to the address which follows random data input command (85h). Random data input may be operated multiple times re-
gardless of how many times it is done in a page. The Page Program confirm command (10h) initiates the programming
process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The inter-
nal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby free-
ing the system controller for other tasks. Once the program process starts, the Read Status Register command may be
entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O
6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress.
When the Page Program is complete, the Write Status Bit (I/O 0) may be checked.
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s.
The command register remains in Read Status command mode until another valid command is written to the command
register. Figure 14 details the sequence.
Rev 0.2 /APR. 2009
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