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PDF USB2230 Data sheet ( Hoja de datos )
| Número de pieza | USB2230 | |
| Descripción | 5th Generation Hi-Speed USB Flash Media and IrDA Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USB2230 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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USB2229/USB2230
5th Generation Hi-Speed USB Flash Media
and IrDA Controller with Integrated Card Power FETs
IrDA Controller
• IrDA v1.1 FIR and SIR Compliant Controller, with
9.6K, 19.2K, 38.4K, 57.6K, 115.2K, 0.576Mbps,
1.152Mpbs and 4Mbps data rate support.
Flash Media Controller
• Complete System Solution for interfacing Smart-
Media™ (SM) or xD Picture Card™ (xD)1, Memory
Stick™ (MS), High Speed Memory Stick (HSMS),
Memory Stick PRO (MSPRO), MS Duo™, Secure
Digital (SD), High Speed SD, Mini-Secure Digital
(Mini-SD), TransFlash (SD), MultiMediaCard™
(MMC), Reduced Size MultiMediaCard (RS-
MMC), NAND Flash, Compact Flash™ (CF) and
CF Ultra™ I & II, and CF form-factor ATA hard
drives to Hi-Speed USB
- Supports USB Bulk Only Mass Storage Com-
pliant Bootable BIOS
• Support for simultaneous operation of all above
devices. (only one at a time of each of the follow-
ing groups supported: CF or ATA drive, SM or XD
or NAND, SD or MMC)
• On-Chip 4-Bit High Speed Memory Stick and MS
PRO Hardware Circuitry
• On-Chip firmware reads and writes High Speed
Memory Stick and MS PRO
• 1-bit ECC correction performed in hardware for
maximum efficiency
• Hardware support for SD Security Command
Extensions
• On-chip power FETs with short circuit protection
for supplying flash media card power
• USB Bus Power Certified
• 3.3 Volt I/O with 5V input tolerance on VBUS/
GPIO3
• Complete USB Specification 2.0 Compatibility for
Bus Powered Operation
- Includes Hi-Speed USB Transceiver
- A Bi-directional Control and two Bi-directional
Bulk Endpoints are provided.
• 8051 8 bit microprocessor
- Provides low speed control functions
- 30 Mhz execution speed at 1 clock per
instruction cycle average
- 12K Bytes of internal SRAM for general pur-
pose scratchpad
1.xD Picture Card not applicable to USB2229.
- 768 Bytes of internal SRAM for general pur-
pose scratchpad or program execution while
re-flashing external ROM
- Two, Double Buffered Bulk Endpoints
- Two, Bi-directional 512 Byte Buffers for Bulk
Endpoints
- 64 Byte RX Control Endpoint Buffer
- 64 Byte TX Control Endpoint Buffer
• Internal or External Program Memory Interface
- 76K Byte Internal Code Space or Optional
128K Byte External Code Space using Flash,
SRAM or EPROM memory.
• On Board 24Mhz Crystal Driver Circuit
• Can be clocked by 48MHz external source
• On-Chip 1.8V Regulator for Low Power Core
Operation
• Internal PLL for 480Mhz Hi-Speed USB Sampling,
Configurable MCU clock
• Supports firmware upgrade via USB bus if “boot
block” Flash program memory is used
• 12 GPIOs for special function use: LED indica-
tors, button inputs, power control to memory
devices, etc.
- Inputs capable of generating interrupts with
either edge sensitivity
• Attribute bit controlled features:
- Activity LED polarity/operation/blink rate
- Full or Partial Card compliance checking
- Bus or Self Powered
- LUN configuration and assignment
- Write Protect Polarity
- SmartDetach - Detach from USB when no
Card Inserted for Notebook apps
- Cover Switch operation for xD compliance
- Inquiry Command operation
- SD Write Protect operation
- Older CF card support
- Force USB 1.1 reporting
- Internal or External Power FET operation
• Compatible with Microsoft WinXP, WinME, Win2K
SP3, Apple OS10, Softconnex, and Linux Multi-
LUN Mass Storage Class Drivers
• Win2K, Win98/98SE and Apple OS8.6 and OS9
Multi-LUN Mass Storage Class Drivers available
from Microchip
• 128-Pin TQFP RoHS Compliant package (1.0mm
height, 14mmx14mm footprint)
2005-2016 Microchip Technology Inc.
DS00002252A-page 1
1 page  
USB2229/USB2230
10. SD Card Specification, Part E1, Secure Digital Input/Output (SDIO) card Specification, Version 1.00, October
2001, SD Group.
11. Memory Stick Standard Excerption from Format Specification v1.3, July, 2000, Sony Corporation.
12. Memory Stick Standard Format Specifications ver 2.0 (Memory Stick PRO). Tentative Release 0.81, February,
2002
13. CompactFlash Specification Rev 1.4
14. CF+ & CF Specification Rev. ATA-5 Draft 0.2
15. Universal Serial Bus Specification Rev 2.0
16. Samsung K9K2G08Q0M Data Sheet
17. xD Picture Card, Card Specification Version 1.10 (Jan 31, 2004)
18. xD Picture Card, Format Specification Version 1.10 (Jan 31, 2004)
19. xD Picture Card, Host Guideline Version 1.10 (Jan 31, 2004)
20. xD Picture Card, Compliance Guideline Version 1.10 (Jan 31, 2004)
2005-2016 Microchip Technology Inc.
DS00002252A-page 5
5 Page 
USB2229/USB2230
5.0 PIN DESCRIPTIONS
This section provides a detailed description of each signal. The signals are arranged in functional groups according to
their associated interface.
The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage
level. When “n” is not present before the signal name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.
5.1 Pin Descriptions
TABLE 5-1: USB2229/USB2230 PIN DESCRIPTIONS
Name
Symbol
Buffer Type
Description
CF Chip Select 1
CF Chip Select 0
CF Register Address
2
CF Register Address
1
CF Register Address
0
CF Interrupt
CF
Data 15-8
CompactFlash (In True IDE Mode) INTERFACE
CF_nCS1
O8PU
This pin is the active low chip select 1 signal for the CF
ATA device
CF_nCS0
O8PU
This pin is the active low chip select 0 signal for the task
file registers of CF ATA device in the True IDE mode.
CF_SA2
O8 This pin is the register select address bit 2 for the CF ATA
device.
CF_SA1
O8 This pin is the register select address bit 1 for the CF ATA
device
CF_SA0
O8 This pin is the register select address bit 0 for the CF ATA
device.
CF_IRQ
IPD This is the active high interrupt request signal from the CF
device.
CF_D[15:8]
I/O8PD The bi-directional data signals CF_D15-CF_D8 in True
IDE mode data transfer.
In the True IDE Mode, all of task file register operation
occur on the CF_D[7:0], while the data transfer is on
CF_D[15:0].
CF
Data7-0
CF_D[7:0]
I/O8PD
The bi-directional data signal has an internal weak pull-
down resistor.
The bi-directional data signals CF_D7-CF_D0 in the True
IDE mode data transfer.
In the True IDE Mode, all of task file register operation
occur on the CF_D[7:0], while the data transfer is on
CF_D[15:0].
IO Ready
CF_IORDY
The bi-directional data signal has an internal weak pull-
down resistor.
IPU This pin is active high input signal.
CF
Card Detection2
CF_nCD2
This pin has an internally controlled weak pull-up resistor.
IPU This card detection pin is connected to the ground on the
CF device, when the CF device is inserted.
CF
Card Detection1
CF_nCD1
This pin has an internally controlled weak pull-up resistor.
IPU This card detection pin is connected to ground on the CF
device, when the CF device is inserted.
CF
Hardware Reset
CF
IO Read
CF_nRESET
CF_nIOR
This pin has an internally controlled weak pull-up resistor.
O8 This pin is an active low hardware reset signal to CF
device.
O8 This pin is an active low read strobe signal for CF device.
2005-2016 Microchip Technology Inc.
DS00002252A-page 11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet USB2230.PDF ] | |
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