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PDF SST25WF080 Data sheet ( Hoja de datos )
| Número de pieza | SST25WF080 | |
| Descripción | 8Mbit 1.8V SPI Serial Flash | |
| Fabricantes | SST | |
| Logotipo |  |
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8Mbit 1.8V SPI Serial Flash
SST25WF080
FEATURES:
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 75 MHz
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 33 MHz)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-bump XFBGA
• All devices are RoHS compliant
PRODUCT DESCRIPTION
The SST25WF080 is a member of the Serial Flash 25
Series family and features a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total sys-
tem costs. SST25WF080 SPI serial flash memory is manu-
factured with SST proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST25WF080 significantly improves performance and
reliability, while lowering power consumption. The device
writes (Program or Erase) with a single power supply of
1.65-1.95V for SST25WF080. The total energy consumed
is a function of the applied voltage, current, and time of
application. Since for any given voltage range, the Super-
Flash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
memory technologies.
The SST25WF080 is offered in both an 8-lead, 150 mils
SOIC package and an 8-bump XFBGA package. See Fig-
ures 2 and 3 for the pin assignments.
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
1
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
8Mbit 1.8V SPI Serial Flash
SST25WF080
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or
a hold pin. From power-on, the RST#/HOLD# pin defaults
as a hardware reset pin (RST#). The Hold mode for this pin
is a user selected option where an Enable-Hold instruction
enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a
HOLD# pin, and goes back to RST# pin only after a power-
off and power-on sequence.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin
provides a hardware method for resetting the device. Driving
the RST# pin high puts the device in normal operating
Advance Information
mode. The RST# pin must be driven low for a minimum of
TRST time to reset the device. The SO pin is in high imped-
ance state while the device is in reset. A successful reset will
reset the status register to its power-up state. See Table 4
for default power-up modes. A device reset during an active
Program or Erase operation aborts the operation and data
of the targeted address range may be corrupted or lost due
to the aborted erase or program operation. The device exits
AAI Programming Mode in progress and places the SO pin
in high impedance state.
CE#
SCK
RST#
SO
SI
TRECR
TRECP
TRECE
TRST
TRHZ
FIGURE 5: Reset Timing Diagram
TABLE 2: Reset Timing Parameters
Symbol
TRST1
TRHZ
TRECR
TRECP
TRECE
Parameter
Reset Pulse Width
Reset to High-Z Output
Reset Recovery from Read
Reset Recovery from Program
Reset Recovery from Erase
Min
100
1. For reset while in a Programming or Erase mode, the reset pulse must be >5µs
1203 F04.0
Max
107
100
10
1
Units
ns
ns
ns
µs
ms
T2.1203
©2010 Silicon Storage Technology, Inc.
5
S71203-03-000
04/10
5 Page 
8Mbit 1.8V SPI Serial Flash
SST25WF080
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
Advance Information
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 9 for the
Byte-Program sequence.
CE#
SCK
MODE 3
MODE 0
012 345 6 78
15 16 23 24 31 32 39
SI 02
MSB
SO
FIGURE 9: Byte-Program Sequence
ADD.
ADD.
ADD. DIN
MSB LSB
HIGH IMPEDANCE
1203 F08.0
©2010 Silicon Storage Technology, Inc.
11
S71203-03-000
04/10
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet SST25WF080.PDF ] | |
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