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PDF FDPC8016S Data sheet ( Hoja de datos )
| Número de pieza | FDPC8016S | |
| Descripción | MOSFET ( Transistor ) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 2013
FDPC8016S
PowerTrench® Power Clip
25V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
Max rDS(on) = 3.8 mΩ at VGS = 10 V, ID = 20 A
Max rDS(on) = 4.7 mΩ at VGS = 4.5 V, ID = 18 A
Q2: N-Channel
Max rDS(on) = 1.4 mΩ at VGS = 10 V, ID = 35 A
Max rDS(on) = 1.7 mΩ at VGS = 4.5 V, ID = 32 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
This device includes two specialized N-Channel MOSFETs in a
dual package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck
converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
PIN1
PIN1
PAD10
V+(HSD)
Top
Power Clip 5X6
Bottom
HSG
GR
V+
V+
PAD9
GND(LSS)
LSG HSG
SW GR
SW V+
SW V+
SW
LSG
SW
SW
SW
Pin Name Description
1 HSG HighSideGate
2 GR
Gate Return
Pin
3,4,10
5,6,7
Name
V+(HSD)
SW
Description
Pin
High Side Drain
8
Switching Node, Low Side Drain 9
Name
Description
LSG
Low Side Gate
GND(LSS) Low Side Source
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
-Pulsed
Single Pulse Avalanche Energy
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
TC = 25 °C
TA = 25 °C
TA = 25 °C (Note 4)
(Note 3)
TC = 25 °C
TA = 25 °C
Q1
25Note5
Q2
25
±12 ±12
60
20Note1a
100
35Note1b
75 140
73 216
21
2.1Note1a
42
2.3 Note1b
-55 to +150
Units
V
V
A
mJ
W
°C
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
6.0
60Note1a
130Note1c
3.0
55Note1b
120Note1d
°C/W
©2013 Fairchild Semiconductor Corporation
FDPC8016S Rev.C7
1
www.fairchildsemi.com
1 page  
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted
10
ID = 20 A
8
VDD = 13 V
6
VDD = 10 V
4
VDD = 15 V
2
0
0 6 12 18 24 30
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
10000
1000
Ciss
100
f = 1 MHz
VGS = 0 V
Coss
Crss
10
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
Figure8. Capacitancevs.Drain
to Source Voltage
30
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
1
0.001
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100
70
60
50
VGS = 10 V
40
VGS = 4.5 V
30
20
RθJC = 6.0 oC/W
10
0
25 50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
500
100
10 μs
10
THIS AREA IS
LIMITED BY rDS(on)
1
SINGLE PULSE
TJ = MAX RATED
RθJC = 6.0 oC/W
TC = 25 oC
CURVE BENT TO
MEASURED DATA
0.1
0.1 1 10
100 μs
1 ms
10 ms
DC
80
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
5000
1000
100
SINGLE PULSE
RθJC = 6.0 oC/W
TC = 25 oC
10
10-5 10-4 10-3 10-2 10-1
t, PULSE WIDTH (sec)
Figure 12. Single Pulse Maximum
Power Dissipation
1
©2013 Fairchild Semiconductor Corporation
FDPC8016S Rev.C7
5
www.fairchildsemi.com
5 Page 
Dimensional Outline and Pad Layout
0.10 C
2X
4
5.10
4.90
PKG
CL
1
PKG CL
PIN #1 5
8
INDICATOR
TOP VIEW
A
B
5.00
4.56
4.20
1.27
43 2
1
1.01
3.30
2.48
2.08
6.10
5.90
0.10 C
2X
6.60
0.00
2.65
0.82
5 6 78
0.75
0.40
0.83
1.43
1.98
2.48
3.30
SEE
DETAIL A
RECOMMENDED LAND PATTERN
SIDE VIEW
3.15±.05
3.81
1.27
56 7 8
0.10
0.05
CAB
C
0.51
0.65±.05
2.46±.05
0.91±.05
0.49±.05
4 32
1
0.51±.05
3.90±.05
4.22±.05
5.00±.05
BOTTOM VIEW
1.57±.05
0.65±.05
1.37±.05
0.53±.05
0.48±.05
NOTES: UNLESS OTHERWISE SPECIFIED
A) DOES NOT FULLY CONFORM TO
JEDEC REGISTRATION, MO-229,
DATED 11/2001.
B) ALL DIMENSIONS ARE IN
MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE
BURRS OR MOLD FLASH. MOLD
FLASH OR BURRS DOES NOT
EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING
PER ASME Y14.5M-1994.
E) DRAWING FILE NAME:
0.10 C
0.08 C
0.80
0.70
0.30 0.05
0.20 0.00
(SCALE: 2X)
C
SEATING
PLANE
©2013 Fairchild Semiconductor Corporation
FDPC8016S Rev.C7
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FDPC8016S.PDF ] | |
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