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PDF USB2601 Data sheet ( Hoja de datos )
| Número de pieza | USB2601 | |
| Descripción | 4th Generation USB 2.0 Flash Media Controller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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USB2601/USB2602
4th Generation USB 2.0 Flash Media Controller with
Integrated Card Power FETs & HS Hub
Hub Controller
• Provides Three USB 2.0 Downstream Ports via
internal USB 2.0 Hub
- Multi Transaction Translator for FS/LS
devices attached
Flash Media Controller
• Complete System Solution for interfacing Smart-
MediaTM (SM) or xD Picture CardTM (xD)1, Mem-
ory StickTM (MS), High Speed Memory Stick
(HSMS), Memory Stick PRO (MSPRO), MS
DuoTM, Secure Digital (SD), Mini-Secure Digital
(Mini-SD), TransFlash (SD), MultiMediaCardTM
(MMC), Reduced Size MultiMediaCard (RS-
MMC), NAND Flash, Compact FlashTM (CF) and
CF UltraTM I & II, and CF form-factor ATA hard
drives to USB 2.0 bus
- Supports USB Bulk Only Mass Storage Com-
pliant Bootable BIOS
• Support for simultaneous operation of all above
devices. (only one at a time of each of the follow-
ing groups supported: CF or ATA drive, SM or XD
or NAND, SD or MMC)
• On-Chip 4-Bit High Speed Memory Stick and MS
PRO Hardware Circuitry
• On-Chip firmware reads and writes High Speed
Memory Stick and MS PRO
• 1-bit ECC correction performed in hardware for
maximum efficiency
• Hardware support for SD Security Command
Extensions
• 3.3 Volt I/O with 5V input tolerance on VBUS, Port
Power and Over-Current Sense pins
• On-chip power FETs for supplying flash media
card power with minimum board components
• 8051 8 bit microprocessor
- Provides low speed control functions
- 30 MHz execution speed at 4 cycles per
instruction average
- 12K Bytes of internal SRAM for general pur-
pose scratchpad
- 768 Bytes of internal SRAM for general pur-
pose scratchpad or program execution while
re-flashing external ROM
- Double Buffered Bulk Endpoint
- Bi-directional 512 Byte Buffer for Bulk End-
point
- 64 Byte RX Control Endpoint Buffer
- 64 Byte TX Control Endpoint Buffer
• Internal Program Memory Interface
- 64K Byte Internal Code Space
• On Board 24MHz Crystal Driver Circuit
• Can be clocked by an external 24MHz source
• On-Chip 1.8V Regulator for Low Power Core
Operation
• Internal PLL for 480MHz USB 2.0 Sampling, Con-
figurable MCU clock
• 11 GPIOs for special function use: LED indicators,
button inputs, power control to memory devices,
etc.
- Inputs capable of generating interrupts with
either edge sensitivity
• Configuration of Hub and Flash Media features
controlled either by internal defaults or via single
external EEPROM. User configurable features:
- Full or Partial Card compliance checking
- LUN configuration and assignment
- Write Protect Polarity
- Cover Switch operation for xD compliance
- Inquiry Command operation
- SD Write Protect operation
- Older CF card support
- Force USB 1.1 reporting
- Internal or External Power FET operation
• Compatible with Microsoft WinXP, WinME, Win2K
SP3&4, Apple OS10 and Linux Multi-LUN Mass
Storage Class Drivers
• Win2K, Win98/98SE and Apple OS8.6 and OS9
Multi-LUN Mass Storage Class Drivers are avail-
able from Microchip
• 128-Pin TQFP Package (1.0mm height, 14mm
x14mm footprint); RoHS compliant package also
available
1.xD Picture Card not applicable to USB2601
2004 - 2016 Microchip Technology Inc.
DS00002119A-page 1
1 page  
USB2601/USB2602
ECC:
CRC:
Error Checking and Correcting
Cyclic Redundancy Checking
1.4 Reference Documents
1. SmartMediaTM Electrical Specification Version 1.30
2. SmartMediaTM Physical Format Specifications Version 1.30
3. SmartMediaTM Logical Format Specifications Version 1.20
4. SMIL (SmartMedia Interface Library) Software Edition Version 1.00, Toshiba Corporation, 01, July, 2000
5. SMIL (SmartMedia Interface Library) Hardware Edition Version 1.00, Toshiba Corporation, 01, July, 2000
6. MultiMediaCard System Specification Version 2.2
7. SD Memory Card Specifications, Part 1, Physical Layer Specification Version 1.10, April 2003, SD Group
8. SD Memory Card Specifications, Part 2, File System Specification Version 1.01, April 15th, 2001, SD Group
9. SD Memory Card Specifications, Part 3, Security Specification Version 1.01, April 15th, 2001, SD Group
10. SD Card Specification, Part E1, Secure Digital Input/Output (SDIO) card Specification, Version 1.00, October
2001, SD Group
11. Memory Stick Standard Excerpt from Format Specification v1.3, July, 2000, Sony Corporation.
12. Memory Stick Standard Format Specifications Version 2.0 (Memory Stick PRO) Tentative Release 0.81, Febru-
ary, 2002
13. CompactFlash Specification Rev. 1.4
14. CF+ & CF Specification Rev. ATA-5 Draft 0.2
15. Universal Serial Bus Specification Rev. 2.0
16. Samsung K9K2G08Q0M Data Sheet
17. xD Picture Card, Card Specification Version 1.10 (Jan 31, 2004)
18. xD Picture Card, Format Specification Version 1.10 (Jan 31, 2004)
19. xD Picture Card, Host Guideline Version 1.10 (Jan 31, 2004)
20. xD Picture Card, Compliance Guideline Version 1.10 (Jan 31, 2004)
2004 - 2016 Microchip Technology Inc.
DS00002119A-page 5
5 Page 
USB2601/USB2602
5.0 PIN DESCRIPTIONS
This section provides a detailed description of each signal. The signals are arranged in functional groups according to
their associated interface.
The “n” or “_N” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low
voltage level. When “n” is not present before the signal name (or “_N” after the signal name), the signal is asserted when
at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of
“active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of
whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.
5.1 PIN Descriptions
Name
USB Bus Data
Detect Upstream
VBUS Power
USB Bus Data
USB Power Enable
Port Power Polarity
Strapping
Over Current Sense
Green LED
CF Chip Select 1
Symbol
USBUP_DM
USBUP_DP
VBUS_DET
Buffer Type
Description
UPSTREAM USB INTERFACE
IO-U
These pins connect to the Upstream USB bus data
signals.
I/O12
Detects state of Upstream VBUS power. The Microchip
Hub monitors VBUS_DET to determine when to assert
the internal D+ pull-up resistor (signalling a connect
event).
When designing a detachable hub, this pin must be
connected to the VBUS power pin of the USB port that is
upstream of the hub.
USBDN_DM
[4:2]
USBDN_DP
[4:2]
PRTPWR[4:2]
For self-powered applications with a permanently
attached host, this pin must be pulled-up to either 3.3V or
5.0V (typically VDD33).
3-PORT USB INTERFACE
IO-U
These pins connect to the Downstream USB bus data
signals.
I/O12 Enables power to USB peripheral devices (downstream).
PRTPWR_POL
I/O12
The active signal level of the PRTPWR[4:2] pins is
determined by the Power Polarity Strapping function of
the PRTPWR_POL pin.
Port Power Polarity strapping determination for the active
signal polarity of the PRTPWR[4:2] pins.
While RESET_N is asserted, the logic state of this pin will
(though the use of internal combinatorial logic) determine
the active state of the PRTPWR[4:2] pins in order to
ensure that downstream port power is not inadvertently
enabled to inactive ports during a hardware reset.
‘1’ = PRTPWR[4:2] pins have an active ‘high’ polarity
‘0’ = PRTPWR[4:2] pins have an active ‘low’ polarity
OCS[4:2]_N
IPU Input from external current monitor indicating an over-
current condition. {Note: Contains internal pull-up to 3.3V
supply}
GR[4:2]_N
I/O8 Green indicator LED for ports 2, 3 and 4. Will be active
low when LED support is enabled via EEPROM or
SMBus.
CompactFlash (In True IDE mode) INTERFACE
CF_nCS1
O8PU
This pin is the active low chip select 1 signal for the CF
ATA device
2004 - 2016 Microchip Technology Inc.
DS00002119A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet USB2601.PDF ] | |
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