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PDF AS8SLC128K32 Data sheet ( Hoja de datos )
| Número de pieza | AS8SLC128K32 | |
| Descripción | 128K x 32 SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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SRAM
AS8SLC128K32
128K x 32 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD-883
FEATURES
• Fast Access Times of 10 to 25ns
• Overall Configuration: 128K x 32
• 4 Low Power CMOS 128K x 8 SRAMs in one MCM
• +3.3V power supply
• Internal Decoupling Capacitors
• Low Operating Power, 1/2 Previous Generation
OPTIONS
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
MARKINGS
XT
IT
• Timing
10ns
12ns
15ns
17ns
20ns
25ns
• Package
Ceramic Quad Flatpack
Pin Grid Array
• Low Power Data Retention Mode
-10
-12
-15
-17
-20
-25
Q
P
L
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60 I/O 16
59 I/O 17
58 I/O 18
57 I/O 19
56 I/O 20
55 I/O 21
54 I/O 22
53 I/O 23
52 GND
51 I/O 24
50 I/O 25
49 I/O 26
48 I/O 27
47 I/O 28
46 I/O 29
45 I/O 30
44 I/O 31
66 Lead PGA (P)
\
CCSS2\
\
NC
\
NC
CCSS1\
CCSS4\
\
\
CCSS3\
GENERAL DESCRIPTION
The AS8SLC128K32 is a high speed, 4MB CMOS SRAM
multichip module (MCM) designed for full temperature range, 3.3V
power supply, military, space, or high reliability mass memory and
fast cache applications.
The device input and output TTL compatible. Writing is executed
when the write enable (WE\) and chip enable (CS\) inputs are low.
Reading is accomplished when WE\ is high and CS\ and output enable
(OE\) are both low. Access time grades of 10ns, 12ns, 15ns, 17ns,
20ns and 25ns maximum are standard.
The products are designed for operation over the temperature
range of -55°C to +125°C and screened under the full military
environment.
FUNCTIONAL BLOCK DIAGRAM
For more products and information
please visit our web site at
www.micross.com
AS8SLC128K32
Rev. 0.8 01/10
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
LOW POWER CHARACTERISTICS (L Version Only)
SRAM
AS8SLC128K32
VCC
CS\ 1-4
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
4.5V
tCDR
VDR > 2V
V
DR
4.5V
tR
NOTES
1. All voltages referenced to VSS (GND).
2. Worst case address switching.
3. ICC is dependent on output loading and cycle rates.
unloaded, and f=
1
t RC(MIN)
HZ.
The specified value applies with the outputs
4. This parameter guaranteed but not tested.
5. Test conditions as specified with output loading as
shown in Fig. 1 & 2 unless otherwise noted.
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in
Fig. 2. Transition is measured +/- 200 mV typical from
steady state voltage, allowing for actual tester RC time
constant.
7. At any given temperature and voltage condition,
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip selects and output
enable are held in their active state.
10. Address valid prior to or coincident with latest occur-
ring chip enable.
11. tRC= READ cycle time.
12. Chip enable (CS\) and write enable (WE\) can initiate
and terminate a WRITE cycle.
13. ICC is for full 32 bit mode.
AS8SLC128K32
Rev. 0.8 01/10
Micross Components reserves the right to change products or specifications without notice.
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AS8SLC128K32.PDF ] | |
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