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PDF AS5LC1008 Data sheet ( Hoja de datos )
| Número de pieza | AS5LC1008 | |
| Descripción | 128K x 8 SRAM | |
| Fabricantes | Micross | |
| Logotipo |  |
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128K x 8 SRAM
High-Speed CMOS SRAM with
3.3V Revolutionary Pinout
FEATURES
• High-speed access times of 10, 12, 15 and 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater noise
immunity
• Easy memory expansion with CE\ and OE\ options
• CE\ power-down
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• RoHS compliant options available
GENERAL DESCRIPTION
OPTIONS
• Timing
10ns access
12ns access
15ns access
20ns access
MARKING
-10
-12
-15
-20
• Package
Plastic SOJ (32-pin, 400-mil)
DJ No. 906
• Operating Temperature Ranges
-Military (-55oC to +125oC)
-Industrial (-40oC to +85oC)
/XT
/IT
• 2V Data Retention / Low Power
L
The AS5LC1008 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The AS5LC1008 is fabricated using high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields higher performance
and low power consumption devices.
When CE\ is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down to 250μW (typical) with CMOS input levels.
The AS5LC1008 operates from a single 3.3V power supply
and all inputs are TTL-compatible.
SRAM
AS5LC1008
PIN ASSIGNMENT
(Top View)
32-Pin, 400-mil
Plastic SOJ (DJ) & Plastic TSOPII (DGC & DGCR)
A0
A1
A2
A3
CE\
I/O 0
I/O 1
Vcc
GND
I/O 2
I/O 3
WE\
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE\
27 I/O 7
26 I/O 6
25 GND
24 Vcc
23 I/O 5
22 I/O 4
21 A12
20 A11
19 A10
18 A9
17 A8
PIN FUNCTIONS
PIN
A0 - A16
CE\
OE\
WE\
I/O0 - I/O7
DESCRIPTION
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
VCC
GND
Power
Ground
For more products and information
please visit our web site at
www.micross.com
AS5LC1008
Rev. 1.4 10/13
Micross Components reserves the right to change products or specifications without notice.
1
1 page  
SRAM
AS5LC1008
DATA RETENTION SWITCHING CHARACTERISTICS (Low Power “L” Version)
Symbol
VDR
IDR
ISDR
IRDR
Parameter
VDDforDataRetention
DataRetentionCurrent
DataRetentionSetupTime
RecoveryTime
TestCondition
SeeDataRetentionWaveform
VDD=2.0V,CE\шVDDͲ0.2V
SeeDataRetentionWaveform
SeeDataRetentionWaveform
Min.
2.0
Ͳ
0
tRC
Typ. Max.
Ͳ 3.6
Ͳ 2
Ͳ Ͳ
Ͳ Ͳ
NOTES:
1. Typical values are measured at VDD=3.0V, TA=25oC and not 100% tested.
DATA RETENTION SWITCHING WAVEFORM (CE\ Controlled)
Unit
V
mA
ns
ns
VDD
VDR
CE
GND
tSDR
Data Retention Mode
tRDR
CE ≥ VDD - 0.2V
AS5LC1008
Rev. 1.4 10/13
Micross Components reserves the right to change products or specifications without notice.
5
5 Page 
SRAM
AS5LC1008
DOCUMENT TITLE
128K x 8 SRAM High-Speed CMOS SRAM with 3.3V Revolutionary Pinout
Rev #
1.2
1.3
1.4
History
Added Micross Information
Release Date
January 2010
Added TSOPII Copper Lead Frame
and RoHS compliant parts, pg 1 &10,
Reduced Power Supply Currents:
Parameter Speed
From (mA)
ICC -10
160
ICC -12
140
ICC -15
130
ICC -20
120
ISB -10
45
ISB -12
40
ISB -15
35
ISB -20
30
ISB1
-10
30
ISB1
-12
30
ISB1
-15
30
ISB1
-20
30
ISB2
-10
10
ISB2
-12
10
ISB2
-15
10
ISB2
-20
10
Added “L” Versions
March 2011
To (mA)
105
100
95
90
35
30
25
20
20
20
20
20
2
2
2
2
Removed Cu-lead frame option
October 2013
Status
Release
Release
Release
AS5LC1008
Rev. 1.4 10/13
11
Micross Components reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet AS5LC1008.PDF ] | |
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