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PDF IR35204 Data sheet ( Hoja de datos )
| Número de pieza | IR35204 | |
| Descripción | 3+1 Dual Output Digital Multi-Phase Controller | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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3+1 Dual Output Digital Multi-Phase Controller
IR35204
FEATURES
Ultra Low Quiescent Power Dual output 3+1 phase
PWM Controller
Intel® VR12 Rev 1.7, VR12.5 Rev 1.5, IMVP8 Rev 1.2,
AMD SVID2, and Memory VR modes
Switching frequency from 194KHz to 2MHz per phase
in 56 steps
IR Efficiency Shaping Features including Dynamic
Phase Control and Automatic Power State Switching
Programmable 1-phase or 2-phase operation for Light
Loads and Active Diode Emulation for very Light
Loads
IR Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Auto-Phase Detection with PID Coefficient auto-
scaling
Fault Protection: OVP, UVP, OCP, OTP, CAT_FLT
I2C/SMBus/PMBus system interface for reporting of
Temperature, Voltage, Current & Power telemetry for
both loops
Multiple Time Programming (MTP) with integrated
charge pump for easy non-volatile programming
Compatible with 3.3V tri-state drivers
+3.3V supply voltage; -40oC to 85oC ambient
operation; -40oC to 125oC junction
Pb-Free, RoHS, 5x5mm 40-pin, 0.4mm pitch QFN
APPLICATIONS
Intel® VR12, VR12.5 and IMVP8 (overclocking only),
AMD SVI2 based systems
Servers and High End Desktop CPU VRs
High Performance Graphics Processors, Memory VR
DESCRIPTION
The IR35204 is a dual-loop digital multi-phase
buck controller designed for CPU voltage
regulation, and is fully compliant with Intel®, VR12
Rev 1.7, VR12.5 Rev 1.5, IMVP82 Rev 1.2, and
AMD SVI2 REV 1.06 specifications.
The IR35204 includes IR’s Efficiency Shaping
Technology to deliver exceptional efficiency at
minimum cost across the entire load range. IR’s
Dynamic Phase Control adds/drops phases based
upon load current. The IR35204 can be configured
to enter 1 or 2-phase PS1 operation and active
diode emulation mode automatically or by
command.
IR’s unique Adaptive Transient Algorithm (ATA),
based on proprietary non-linear digital PWM
algorithms, minimizes output bulk capacitors.
IR35204 has 127 possible address values for both
the PMBus and I2C bus interfaces. The device
configuration can be easily defined using the IR
PowIRCenter GUI, and is stored in the on-chip
Non-Volatile Memory (NVM). This reduces external
components and minimizes the package size.
The IR35204 provides extensive OVP, UVP, OCP,
OTP & CAT_FLT fault protection, and includes
thermistor based temperature sensing or per
phase temperature reporting when using the IR
powIRstage. The controller is designed to work
with either Rdson current sense PowIRstages or
with DCR current sense.
The IR35204 also includes numerous VR design
simplifying and differentiating features, like register
diagnostics, which enable fast time-to-market.
ORDERING INFORMATION
Base Part
Number
IR35204
Package Type
40-pin, QFN 5 mm x 5 mm
Standard Pack
Form
Quantity
Tape and Reel
3000
Orderable
Part Number
IR35204MxxyyTRP1
IR35204
40-pin, QFN 5 mm x 5 mm
Tape and Reel
3000
IR35204MTRPBF
IR35204
40-pin, QFN 5 mm x 5 mm
Tray
4900
IR35204MTYPBF
Notes:
1.
2.
Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing).
IR35204 is not intended for application where ultra low power PS4 shutdown functionality is required.
1 www.irf.com | © 2016 International Rectifier
February 8, 2016 | V1.6
1 page  
3+1 Dual Output Digital Multi-Phase Controller
IR35204
PIN DESCRIPTIONS
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN NAME
RCSM
VRDY2
VSEN
VRTN
I_IN
TSEN1
CFILT
VRDY1
EN_L2
PWROK
CAT_FLT
VINSEN
SV_ADDR
VDDIO
SV_ALERT#
SVT
SV_CLK
SV_DIO
VRHOT_ICRIT#
EN
ADDR_PROT
SM_ALERT#
TYPE
PIN DESCRIPTION
A [O]
D [O]
A [I]
A [I]
A [I]
A [I]
A [O]
D [O]
D[I]
D[I]
D[O]
A [I]
A[I]
A[P]
D [O]
D [I]
D [B]
D [O]
D [I]
D [B]/
D [O]
Resistor Current Sense Minus Loop#1. This pin is connected to an external network to set the
load line slope, bandwidth and temperature compensation for Loop 1.
Voltage Regulator Ready Output (Loop #2). Open-drain output that asserts high when the VR
has completed soft-start to Loop #2 boot voltage. Pull-up to an external voltage through a
resistor.
Voltage Sense Input Loop#1. This pin is connected directly to the VR output voltage of Loop #1
at the load and should be routed differentially with VRTN.
Voltage Sense Return Input Loop#1. This pin is connected directly to Loop#1 ground at the
load and should be routed differentially with VSEN.
I in. Input current signal that ranges from 0 to 1Vdc indicating a maximum input current of 62.5A.
Temperature Sense Input Loop 1. An NTC network or the temperature reporting output from an
IR PowIRstage can be connected to this pin to measure temperature for VRHOT and OTP
shutdown. When connected to the IR PowIRstage’s temperature output; the scaled input voltage
to the controller needs to be at a gain of 4.88mV per degC and an offset of 0.365 Vdc so the
controller can correctly report temperature. Typically a 10kohm and 6.39kohm resistive divider is
used to accomplish the scaling between the power stage and the controller.
1.8V Decoupling. A 1F capacitor on this pin provides decoupling for the internal 1.8V supply.
Voltage Regulator Ready Output (Loop #1). Open-drain output that asserts high when the VR
has completed soft-start to Loop #1 boot voltage. Pull-up to an external voltage through a
resistor.
Enable Input for Loop #2. This pin may be configured as an Enable input for loop #2.
Power OK Input (AMD). An input that when low indicates to return to the Boot voltage and when
high indicates to use the SVI bus.
Catastrophic Fault Output Pin. This pin may be used as a Catastrophic Fault CMOS Output Pin
that is driven to VCC under output OVP, NVM CRC errors or a TSEN fault input.
Voltage Sense Input. This is used to detect and measure a valid input supply voltage (typically
4.5V-13.2V) to the VR.
Serial VID Address. If present, a resistor to ground sets the offset to the SVID address set in
NVM. If not, the value stored in NVM is used. Requires a 0.01µF to ground for noise filtering.
VDDIO Input (AMD). This pin provides the voltage to which the SVT line and the SVD
Acknowledge are driven high.
Serial VID ALERT# (INTEL). SVID ALERT# is pulled low by the controller to alert the CPU of
new VR/12/12.5 Status. Pull-up to an external voltage through a resistor.
SVI Telemetry Output (AMD). Telemetry and VOTF information output by the IR35204
Serial VID Clock Input. Clock input driven by the CPU Master.
Serial VID Data I/O. Is a bi-directional serial line over which the CPU Master issues commands to
slave/s and receives data back.
VRHOT_ICRIT# Output. Active low alert pin that can be programmed to assert if temperature or
average load current exceeds user-definable thresholds. Pull-up to an external voltage through a
resistor.
VR Enable Input. ENABLE is used to power-on the regulator, provided Vin and Vcc are present.
ENABLE is not pulled up in the controller. The polarity of the chip enable function is bit-settable to
either an active high or an active low configuration. When the controller is disabled, the controller
de-asserts VR READY and shuts down the regulator. ENABLE pin cannot be left
floating. ENABLE pin must be pulled high or low.
Bus Address & I2C Bus Protection. A resistor to ground on this pin sets the offset to the NVM
value of the I2C address if configured to do so. Subsequently, this pin becomes a logic input to
enable or disable communication on the I2C bus when protection is enabled. Requires a 0.01µF
to ground for noise filtering.
SMBus/PMBus Alert Line. Active low alert pin to indicate that the regulator status has changed.
Requires a pull-up. Ground if not used.
5 www.irf.com | © 2016 International Rectifier
February 8, 2016 | V1.6
5 Page 
3+1 Dual Output Digital Multi-Phase Controller
IR35204
PARAMETER
Vin Accuracy Reporting
Vin Resolution Reporting -PMBUS1
Vin Resolution Reporting –I2C1
Vout Range Reporting1
Vout Accuracy Reporting1
Vout Resolution Reporting-PMBUS1
Vout Resolution Reporting-I2C1
Iout Per Phase Range Reporting1
Iout Accuracy Reporting1
SYMBOL
Loop1 Iout Resolution Reporting-
PMBUS 1
Loop2 Iout Resolution Reporting-
PMBUS 1
Loop1 Iout Resolution Reporting-I2C 1
Loop2 Iout Resolution Reporting-I2C 1
Loop1 Iin Resolution Reporting-PMBUS
1
Loop2 Iin Resolution Reporting-PMBUS
1
Loop1 Iin Resolution Reporting-I2C1
Loop2 Iin Resolution Reporting-I2C1
P_in Resolution Reporting-PMBUS1
P_out Resolution Reporting-PMBUS1
Temperature Range Reporting1
Temperature Accuracy Reporting1
Temperature Range Reporting1
Temperature Accuracy Reporting1
Temperature Resolution Reporting1
Fault Protection
OVP Threshold During Start-up
(until output reaches 1V)
OVP Operating Threshold1
(programmable)
OVP Filter Delay1
Output UVP Threshold1
(programmable)
CONDITIONS
With 1% resistors
No load-line
Vout < 2V
Vout < 4V
Maximum load, all phase
active (based on DCR,
NTC and # active phases)
MIN
-2
-
-
-
-
-
0
-
*0.5A if >255.75A
-
TYP
-
31.25
125
-
±0.5
1.95
15.6
-
±2
0.25*
MAX UNIT
+2 %
- mV
- mV
4V
%
- mV
- mV
62 A
-%
-A
- 0.25 - A
-1
-A
- 0.5 - A
- 31.25 - mA
- 31.25 - mA
- 0.125
-
- 0.0625 -
- 0.5
-
- 0.5
-
IR3555 mode
0 - 158
IR3555 mode
3.5 -
3.5
0 - 134
At 100°C, with ideal NTC -4
-
4
-1
-
A
A
W
W
°C
%
°C
%
°C
Selectable
Relative to VID
Relative to VID
1.2,
-
1.275,
1.35,
2.5
-
V
-
50 to
400
-
mV
- 160
- ns
-
50 to
400
-
mV
11 www.irf.com | © 2016 International Rectifier
February 8, 2016 | V1.6
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IR35204.PDF ] | |
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