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HY57V28820HCTのメーカーはHynix Semiconductorです、この部品の機能は「4Banks x 4M x 8bits Synchronous DRAM」です。 |
部品番号 | HY57V28820HCT |
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部品説明 | 4Banks x 4M x 8bits Synchronous DRAM | ||
メーカ | Hynix Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとHY57V28820HCTダウンロード(pdfファイル)リンクがあります。 Total 14 pages
HY57V28820HC(L)T
4Banks x 4M x 8bits Synchronous DRAM
0.1 : Hynix Change
0.2 : Burst read single write mode correction
Rev. 0.2 / Aug. 2001
1
1 Page PIN CONFIGURATION
HY57V28820HC(L)T
4Banks x 4M x 8bits Synchronous DRAM
VDD 1
54 VSS
DQ0 2
53 DQ7
VDDQ 3
52 VSSQ
NC 4
51 NC
DQ1 5
50 DQ6
VSSQ 6
49 VDDQ
NC 7
48 NC
DQ2 8
47 DQ5
VDDQ 9
46 VSSQ
NC 10
45 NC
DQ3 11
44 DQ4
VSSQ 12
43 VDDQ
NC 13 54pin TSOP II 42 NC
VDD 14 400mil x 875mil 41 VSS
NC 15 0.8mm pin pitch 40 NC
/WE 16
39 DQM
/CAS 17
38 CLK
/RAS 18
37 CKE
/CS 19
36 NC
BA0 20
35 A11
BA1 21
34 A9
A10/AP 22
33 A8
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VDD 27
28 VSS
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
DQM
DQ0 ~ DQ7
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.2 / Aug. 2001
3
3Pages CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Pin
Input Capacitance
CLK
A0 ~ A11, BA0, BA1, CKE,
CS, RAS, CAS, WE, DQM
Data Input / Output Capacitance DQ0 ~ DQ7
OUTPUT LOAD CIRCUIT
HY57V28820HC(L)T
4Banks x 4M x 8bits Synchronous DRAM
Symbol
CI1
CI2
-6/K/H
Min.
2.5
2.5
Max.
3.5
3.8
-8/P/S
Min.
2.5
2.5
Max.
4
5
Unit
pF
pF
CI/O 4 6.5 4 6.5 pF
Output
Vtt=1.4V
RT=250 Ω
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Symbol
ILI
ILO
VOH
VOL
Min.
-1
-1
2.4
-
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
IOH = -2mA
IOL =+2mA
Rev. 0.2 / Aug. 2001
6
6 Page | |||
ページ | 合計 : 14 ページ | ||
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PDF ダウンロード | [ HY57V28820HCT データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
HY57V28820HCLT | 4Banks x 4M x 8bits Synchronous DRAM | Hynix Semiconductor |
HY57V28820HCT | 4Banks x 4M x 8bits Synchronous DRAM | Hynix Semiconductor |
HY57V28820HCT-L | (HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM | Hynix Semiconductor |