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PDF AD7124-8 Data sheet ( Hoja de datos )
| Número de pieza | AD7124-8 | |
| Descripción | Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
8-Channel, Low Noise, Low Power, 24-Bit,
Sigma-Delta ADC with PGA and Reference
AD7124-8
FEATURES
3 power modes
RMS noise
Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical)
Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical)
Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical)
Up to 22 noise free bits in all power modes (gain = 1)
Output data rate
Full power: 9.38 SPS to 19,200 SPS
Mid power: 2.34 SPS to 4800 SPS
Low power: 1.17 SPS to 2400 SPS
Rail-to-rail analog inputs for gains > 1
Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle
settling)
Diagnostic functions (which aid safe integrity level (SIL)
certification)
Crosspoint multiplexed analog inputs
8 differential/15 pseudo differential inputs
Programmable gain (1 to 128)
Band gap reference with 15 ppm/°C drift maximum (70 µA)
Matched programmable excitation currents
Internal clock oscillator
On-chip bias voltage generator
Low-side power switch
General-purpose outputs
Multiple filter options
Internal temperature sensor
Self and system calibration
Sensor burnout detection
Automatic channel sequencer
Per channel configuration
Power supply: 2.7 V to 3.6 V and ±1.8 V
Independent interface power supply
Power-down current: 5 µA maximum
Temperature range: −40°C to +125°C
32-lead LFCSP
3-wire or 4-wire serial interface
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
ESD: 4 kV
APPLICATIONS
Temperature measurement
Pressure measurement
Industrial process control
Instrumentation
Smart transmitters
FUNCTIONAL BLOCK DIAGRAM
AVDD REGCAPA
REFOUT
REFIN1(+) REFIN1(–)
IOVDD REGCAPD
AIN0/IOUT/VBIAS
AIN1/IOUT/VBIAS
AIN2/IOUT/VBIAS/P1
AIN3/IOUT/VBIAS/P2
AIN4/IOUT/VBIAS/P3
AIN5/IOUT/VBIAS/P4
AIN6/IOUT/VBIAS
AIN7/IOUT/VBIAS
AIN8/IOUT/VBIAS
AIN9/IOUT/VBIAS
AIN10/IOUT/VBIAS
AIN11/IOUT/VBIAS
AIN12/IOUT/VBIAS
AIN13/IOUT/VBIAS
AIN14/IOUT/VBIAS/REFIN2(+)
AIN15/IOUT/VBIAS/REFIN2(–)
PSW
1.9V
LDO
VBIAS
CROSSPOINT
MUX
BANDGAP
REF
AVDD
BURNOUT
DETECT
PGA1
X-MUX
AVSS
AVDD
AVSS
AVSS
REFIN2(+)
REFIN2(–)
1.8V
LDO
PGA2
BUF
BUF
24-BIT
Σ-Δ ADC
REFERENCE
BUFFERS
VARIABLE
DIGITAL
FILTER
SERIAL
INTERFACE
AND
CONTROL
LOGIC
ANALOG
BUFFERS
CHANNE L
SEQUENCER
TEMPERATURE
SENSOR
DIAGNOSTICS
POWER
SWITCH
AVSS
EXCITATION
CURRENTS
GPOs
AVDD
DIAGNOSTICS
COMMUNICATIONS
POWER SUPPLY
SIGNAL CHAIN
DIGITAL
AVSS
Figure 1.
DGND
INTERNAL
CLOCK
AD7124-8
DOUT/RDY
DIN
SCLK
CS
SYNC
CLK
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7124-8
Data Sheet
GENERAL DESCRIPTION
The AD7124-8 is a low power, low noise, completely integrated
analog front end for high precision measurement applications.
The device contains a low noise, 24-bit Σ-Δ analog-to-digital
converter (ADC), and can be configured to have 8 differential
inputs or 15 single-ended or pseudo differential inputs. The on-
chip low gain stage ensures that signals of small amplitude can
be interfaced directly to the ADC.
One of the major advantages of the AD7124-8 is that it gives the
user the flexibility to employ one of three integrated power
modes. The current consumption, range of output data rates,
and rms noise can be tailored with the power mode selected.
The device also offers a multitude of filter options, ensuring that
the user has the highest degree of flexibility.
The AD7124-8 can achieve simultaneous 50 Hz and 60 Hz
rejection when operating at an output data rate of 25 SPS (single
cycle settling), with rejection in excess of 80 dB achieved at lower
output data rates.
The AD7124-8 establishes the highest degree of signal chain
integration. The device contains a precision, low noise, low
drift internal band gap reference and accepts an external
differential reference, which can be internally buffered. Other
key integrated features include programmable low drift excitation
current sources, burnout currents, and a bias voltage generator,
which sets the common-mode voltage of a channel to AVDD/2.
The low-side power switch enables the user to power down
bridge sensors between conversions, ensuring the absolute
minimal power consumption of the system. The device also
allows the user the option of operating with either an internal
clock or an external clock.
The integrated channel sequencer allows several channels to be
enabled simultaneously, and the AD7124-8 sequentially converts
on each enabled channel, simplifying communication with the
device. As many as 16 channels can be enabled at any time, a
channel being defined as an analog input or a diagnostic such
as a power supply check or a reference check. This unique
feature allows diagnostics to be interleaved with conversions.
The AD7124-8 also supports per channel configuration. The
device allows eight configurations or setups. Each configuration
consists of gain, filter type, output data rate, buffering, and
reference source. The user can assign any of these setups on a
channel by channel basis.
The AD7124-8 also has extensive diagnostic functionality
integrated as part of its comprehensive feature set. These
diagnostics include a cyclic redundancy check (CRC), signal
chain checks, and serial interface checks, which lead to a more
robust solution. These diagnostics reduce the need for external
components to implement diagnostics, resulting in reduced
board space needs, reduced design cycle times, and cost savings.
The failure modes effects and diagnostic analysis (FMEDA) of a
typical application has shown a safe failure fraction (SFF) greater
than 90% according to IEC 61508.
The device operates with a single analog power supply from 2.7 V
to 3.6 V or a dual 1.8 V power supply. The digital supply has a
range of 1.65 V to 3.6 V. It is specified for a temperature range
of −40°C to +125°C. The AD7124-8 is housed in a 32-lead
LFCSP package.
Note that, throughout this data sheet, multifunction pins, such
as DOUT/RDY, are referred to either by the entire pin name or
by a single function of the pin, for example, RDY, when only
that function is relevant.
Table 1. AD7124-8 Overview
Parameter
Maximum Output Data Rate
RMS Noise (Gain = 128)
Peak-to-Peak Resolution at 1200 SPS
(Gain = 1)
Typical Current (ADC + PGA)
Low Power Mode
2400 SPS
24 nV
16.4 bits
255 µA
Mid Power Mode
4800 SPS
20 nV
17.1 bits
355 µA
Full Power Mode
19,200 SPS
23 nV
18 bits
930 µA
Rev. D | Page 4 of 92
5 Page 
AD7124-8
Data Sheet
Parameter1
POWER-DOWN CURRENTS13
Standby Current
IAVDD
IIOVDD
Power-Down Current
IAVDD
IIOVDD
Min Typ
7
8
1
1
Max Unit Test Conditions/Comments
Independent of power mode
15 µA LDOs on only
20 µA
3 µA
2 µA
1 Temperature range = −40°C to +125°C.
2 These specifications are not production tested but are supported by characterization data at the initial product release.
3 FS is the decimal equivalent of the FS[10:0] bits in the filter registers.
4 The nonlinearity is production tested in full power mode. For the other power modes, this specification is supported by characterization data at the initial product
release.
5 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-
scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.
6 Recalibration at any temperature removes these errors.
7 Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, TA = 25°C.
8 When gain > 1, the common-mode voltage is between (AVSS + 0.1 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
9 Specification is for a wider common-mode voltage between (AVSS − 0.05 + 0.5/gain) and (AVDD − 0.1 − 0.5/gain).
10 REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and
60 Hz rejection.
11 When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.
12 When VREF = (AVDD − AVSS), the typical differential input equals 0.92 × VREF/gain for the low and mid power modes and 0.86 × VREF/gain for full power mode.
13 The digital inputs are equal to IOVDD or DGND with excitation currents and bias voltage generator disabled.
TIMING CHARACTERISTICS
AVDD = 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOVDD = 1.65 V to 3.6 V, AVSS = DGND = 0 V, Input
Logic 0 = 0 V, Input Logic 1 = IOVDD, unless otherwise noted.
Table 3.
Parameter1, 2
t3
t4
t12
t13
Min
100
100
3/MCLK3
12/MCLK
24/MCLK
t14
READ OPERATION
t1
t24
t56, 7
t6
t78
3/MCLK
12/MCLK
24/MCLK
0
0
10
0
10
110
t7A7 t5
Typ
6
25
50
Max Unit
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
ns
80 ns
80 ns
80 ns
ns
ns
ns
ns
Test Conditions/Comments
SCLK high pulse width
SCLK low pulse width
Delay between consecutive read/write operations
Full power mode
Mid power mode
Low power mode
DOUT/RDY high time if DOUT/RDY is low and the next
conversion is available
Full power mode
Mid power mode
Low power mode
SYNC low pulse width
Full power mode
Mid power mode
Low power mode
CS falling edge to DOUT/RDY active time
SCLK active edge5 to data valid delay
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
The DOUT_RDY_DEL bit is cleared, the CS_EN bit is
cleared
The DOUT_RDY_DEL bit is set, the CS_EN bit is cleared
Data valid after CS inactive edge, the CS_EN bit is set
Rev. D | Page 10 of 92
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7124-8.PDF ] | |
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