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AD9559 の電気的特性と機能

AD9559のメーカーはAnalog Devicesです、この部品の機能は「Multiservice Line Card Adaptive Clock Translator」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9559
部品説明 Multiservice Line Card Adaptive Clock Translator
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9559 Datasheet, AD9559 PDF,ピン配置, 機能
Data Sheet
Dual PLL, Quad Input, Multiservice
Line Card Adaptive Clock Translator
AD9559
FEATURES
Supports GR-1244 Stratum 3 stability in holdover mode
Supports smooth reference switchover with virtually
no disturbance on output phase
Supports Telcordia GR-253 jitter generation, transfer, and
tolerance for SONET/SDH up to OC-192 systems
Supports ITU-T G.8262 synchronous Ethernet slave clocks
Supports ITU-T G.823, G.824, G.825, and G.8261
Auto/manual holdover and reference switchover
Adaptive clocking allows dynamic adjustment of feedback
dividers for use in OTN mapping/demapping applications
Dual digital PLL architecture with four reference inputs
(single-ended or differential)
4x2 crosspoint allows any reference input to drive either PLL
Input reference frequencies from 2 kHz to 1250 MHz
Reference validation and frequency monitoring (2 ppm)
Programmable input reference switchover priority
20-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/HSTL output or as 2 single-ended
CMOS outputs
Output frequencies: 262 kHz to 1250 MHz
Programmable 17-bit integer and 23-bit fractional
feedback divider in digital PLL
Programmable digital loop filter covering loop bandwidths
from 0.1 Hz to 2 kHz
Low noise system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Pin program function for easy frequency translation
configuration
Software controlled power-down
72-lead (10 mm × 10 mm) LFCSP package
APPLICATIONS
Network synchronization, including synchronous Ethernet
and SDH to OTN mapping/demapping
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 3 holdover, jitter cleanup, and phase transient
control
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9559 is a low loop bandwidth clock multiplier that
provides jitter cleanup and synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9559 generates an output clock synchronized to up to four
external input references. The digital PLL allows for reduction
of input time jitter or phase noise associated with the external
references. The digitally controlled loop and holdover circuitry
of the AD9559 continuously generates a low jitter output clock
even when all reference inputs have failed.
The AD9559 operates over an industrial temperature range of
−40°C to +85°C. If a single DPLL version of this part is needed,
refer to the AD9557.
FUNCTIONAL BLOCK DIAGRAM
AD9559
CHANNEL 0A
DIVIDER
REFERENCE
INPUT
MONITOR
AND MUX
DIGITAL
PLL 0
ANALOG
PLL 0
DIGITAL
PLL 1
ANALOG
PLL 1
CLOCK
MULTIPLIER
EEPROM
SERIAL INTERFACE
(SPI OR I2C)
÷3 TO ÷11
HF DIVIDER 0
÷3 TO ÷11
HF DIVIDER 1
STATUS AND
CONTROL PINS
CHANNEL 0B
DIVIDER
CHANNEL 1A
DIVIDER
CHANNEL 1B
DIVIDER
STABLE
SOURCE
Figure 1.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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AD9559 pdf, ピン配列
AD9559
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital PLL (DPLL) Core .......................................................... 34
Applications....................................................................................... 1
Loop Control State Machine..................................................... 36
General Description ......................................................................... 1
System Clock (SYSCLK)................................................................ 37
Functional Block Diagram .............................................................. 1
SYSCLK Inputs ........................................................................... 37
Revision History ............................................................................... 3
SYSCLK Multiplier..................................................................... 37
Specifications..................................................................................... 4
Output PLL (APLL) ....................................................................... 39
Supply Voltage............................................................................... 4
APLL Configuration .................................................................. 39
Supply Current.............................................................................. 4
APLL Calibration ....................................................................... 39
Power Dissipation......................................................................... 5
Clock Distribution.......................................................................... 40
System Clock Inputs (XOA, XOB) ............................................. 5
Clock Dividers ............................................................................ 40
Reference Inputs ........................................................................... 6
Output Enable............................................................................. 40
Reference Monitors ...................................................................... 7
Output Mode and Power-Down .............................................. 40
Reference Switchover Specifications.......................................... 7
Distribution Clock Outputs ........................................................ 8
Clock Distribution Synchronization........................................ 41
Status and Control.......................................................................... 42
Time Duration of Digital Functions ........................................ 10
Digital PLL (DPLL_0 and DPLL_1) ........................................ 10
Multifunction Pins (M0 to M5) ............................................... 42
IRQ Function .............................................................................. 42
Analog PLL (APLL_0 and APLL_1) ........................................ 10
Watchdog Timer......................................................................... 43
Digital PLL Lock Detection ...................................................... 10
EEPROM ..................................................................................... 43
Holdover Specifications............................................................. 10
Serial Control Port ......................................................................... 49
Serial Port Specifications—SPI Mode...................................... 11
Serial Port Specifications—I2C Mode ...................................... 12
SPI/I²C Port Selection................................................................ 49
SPI Serial Port Operation .......................................................... 49
Logic Inputs (RESET, M5 to M0)............................................. 12
Logic Outputs (M5 to M0)........................................................ 12
Jitter Generation ......................................................................... 13
Absolute Maximum Ratings.......................................................... 16
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions........................... 17
Typical Performance Characteristics ........................................... 20
Input/Output Termination Recommendations .......................... 26
Getting Started ................................................................................ 27
Chip Power Monitor and Startup............................................. 27
Multifunction Pins at Reset/Power-Up ................................... 27
Device Register Programming Using a Register Setup File.. 27
Register Programming Overview............................................. 28
Theory of Operation ...................................................................... 31
Overview...................................................................................... 31
Reference Input Physical Connections.................................... 32
Reference Monitors .................................................................... 32
Reference Input Block................................................................ 32
Reference Switchover ................................................................. 33
I²C Serial Port Operation .......................................................... 53
Programming the I/O Registers ................................................... 56
Buffered/Active Registers.......................................................... 56
Write Detect Registers ............................................................... 56
Autoclear Registers..................................................................... 56
Register Access Restrictions...................................................... 56
Thermal Performance.................................................................... 57
Power Supply Partitions................................................................. 58
3.3 V Supplies.............................................................................. 58
1.8 V Supplies.............................................................................. 58
Bypass Capacitors for Pin 21 and Pin 33................................. 58
Register Map ................................................................................... 59
Register Map Bit Descriptions ...................................................... 72
Serial Control Port Configuration (Register 0x0000 to
Register 0x0005) ......................................................................... 72
Clock Part Family ID (Register 0x000C and Register 0x000D) 72
User Scratchpad (Register 0x000E and Register 0x000F)..... 73
General Configuration (Register 0x0100 to Register 0x0109) .. 73
IRQ Mask (Register 0x010A to Register 0x112) .................... 74
Rev. C | Page 2 of 120


3Pages


AD9559 電子部品, 半導体
Data Sheet
AD9559
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION
Typical Configuration
Min
0.57
All Blocks Running
Full Power-Down
Incremental Power Dissipation
Complete DPLL/APLL On/Off
0.71
171
Input Reference On/Off
Differential Without Divide-by-2
Differential With Divide-by-2
Single-Ended (Without Divide-by-2)
Output Distribution Driver On/Off
LVDS (at 750 MHz)
HSTL (at 750 MHz)
1.8 V CMOS (at 250 MHz)
3.3 V CMOS (at 250 MHz)
19
25
5
12
14
14
18
SYSTEM CLOCK INPUTS (XOA, XOB)
Table 4.
Parameter
SYSTEM CLOCK MULTIPLIER
PLL Output Frequency Range
Min
750
Phase Frequency Detector (PFD) Rate
Frequency Multiplication Range
SYSTEM CLOCK REFERENCE INPUT PATH
Input Frequency Range
Minimum Input Slew Rate
4
10
50
Common-Mode Voltage
Differential Input Voltage Sensitivity
1.05
250
System Clock Input Doubler Duty Cycle
System Clock input = 50 MHz
System Clock input = 20 MHz
System Clock input = 16 MHz to 20 MHz
Input Capacitance
Input Resistance
45
46
47
Typ Max Unit
0.71 0.85 W
0.89 1.1 W
75 110 mW
214 257 mW
25 31
32 39
6.6 8
17 22
21 28
21 28
27 36
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
System clock: 49.152 MHz crystal; two DPLLs active;
two 19.44 MHz input references in differential mode;
two HSTL drivers at 644.53125 MHz; two 3.3 V CMOS
drivers at 161.1328125 MHz and 80 pF capacitive load
on CMOS output
System clock: 49.152 MHz crystal; two DPLLs active,
all input references in differential mode; two HSTL
drivers at 750 MHz; four 3.3 V CMOS drivers at 250 MHz
and 80 pF capacitive load on CMOS outputs
Typical configuration with no external pull-up or pull-
down resistors; about 2/3 of this power is on VDD3
Typical configuration; table values show the change in
power due to the indicated operation
This power delta is computed relative to the typical
configuration; the blocks powered down include one
reference input, one DPLL, one APLL, one P divider, two
channel dividers, one HSTL driver, and one CMOS driver;
roughly 2/3 of the power savings is on the 1.8 V supply
Additional current draw is in the VDD3 domain only
Additional current draw is in the VDD3 domain only
Additional current draw is in the VDD3 domain only
Additional current draw is in the VDD domain only
Additional current draw is in the VDD domain only
A single 1.8 V CMOS output with an 80 pF load
A single 3.3 V CMOS output with an 80 pF load
Typ Max Unit Test Conditions/Comments
805 MHz
150 MHz
255
VCO range may place limitations on nonstandard system
clock input frequencies
Assumes valid system clock and PFD rates
400 MHz
V/μs
1.16 1.27 V
mV p-p
50 55 %
50 54 %
50 53 %
3 pF
4.1 kΩ
Rev. C | Page 5 of 120
Minimum limit imposed for jitter performance; jitter
performance affected if sine wave input ≤ 20 MHz
Internally generated
Minimum voltage across pins required to ensure switching
between logic states; the instantaneous voltage on either
pin must not exceed supply rails; single-ended input can
be accommodated by ac grounding complementary input;
1 V p-p recommended for optimal jitter performance
Amount of duty cycle variation that can be tolerated on
the system clock input to use the doubler
Single-ended, each pin

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