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PDF HI-8429 Data sheet ( Hoja de datos )
| Número de pieza | HI-8429 | |
| Descripción | 8-Channel GND/Open or Supply/Open Sensor | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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November 2015
HI-8429
8-Channel GND/Open or Supply/Open Sensor
with Programmable Thresholds and SPI Interface
GENERAL DESCRIPTION
The HI-8429 is an 8-channel discrete-to-digital sensor
fabricated with Silicon-on-Insulator (SOI) technology
designed to interface with a Serial Peripheral Interface
(SPI).
Each input is individually configurable as either GND/Open
or Supply/Open (28V/Open). Discrete input thresholds are
programmable in the range of 2V to 12V. An SPI bus is
used to configure the sensors and to read sensor data .
The part operates from a 3.3V (±5%) digital supply and
12V to 15V analog supply.
A 1mA wetting current is sourced from the input network on
each SENSE input when GND/Open mode is selected for
that pin. The wetting current serves to prevent dry relay or
switch contacts. An optional debounce circuit also ensures
sensor outputs respond correctly to mechanical sensor
inputs. A sensor output interrupt pin alerts the system to a
change in sensor input, avoiding constant polling via SPI to
check status.
All sense inputs are internally lightning protected to
RTCA/DO160G, Section 22 Level 3 Pin Injection Test
Waveform Set A(3 & 4), Set B (3 & 5A) and Set Z (3 & 5B)
without the using external components.
Higher levels of lightning protection can be achieved with
an external series resistor and transorb at each SENSE
input, refer to AN305 for more details.
APPLICATION
· Avionics Discrete to Digital Sensing
FEATURES
· Robust CMOS Silicon-on-Insulator (SOI) technology
· Eight discrete inputs, individually configurable as
GND/Open or Supply/Open
· Interrupt generated on any change of sensor state
· SPI programmable sensor thresholds
· Sensor data read through SPI bus
· Airbus ABD0100H specification compliant
· MIL-STD-704 compliant
· Sense inputs lightning protected to RTCA/DO1060G,
Section 22 Level 3
· 10MHz Serial Peripheral Interface (SPI) allows daisy-
chaining of parts for efficient board routing
· Withstands inadvertent application of 115V AC/400Hz
power to Sense inputs.
· Internal Self-Test mode checks analog comparators
PIN CONFIGURATION
DNBC 1
SENSE1 2
SENSE2 3
SENSE3 4
SENSE4 5
SENSE5 6
SENSE6 7
SENSE7 8
SENSE8 9
INT 10
HI-8429PSx
20 SEL1
19 VDD
18 GND
17 VLOGIC
16 SEL0
15 SI
14 CS
13 SCK
12 SO
11 MR
20-Pin Plastic Small Outline
Wide-body Package
(DS8429 Rev. C)
HOLT INTEGRATED CIRCUITS
www.holtic.com
11/15
1 page  
HI-8429
SUPPLY/OPEN SENSING
When programmed as Supply/Open sensors, CRn is set to a
logic 0. Referring to Figure 1, a switch in series with a diode
is closed to provide a pull down to ground of 30kΩ. As with
GND/Open, Supply/Open sensor levels are set by DAC
thresholds VLO and VHI.
mode, the host should set the sensor outputs to
their pre-test values by writing bits CR8 - CR1 with
their corresponding Data Register pre-test values
recorded in step 2) above.
4) Normal operation (CR9 = 0) is restored by writing
the Configuration Register with its pre-test value
stored in step 1).
WETTING CURRENT
DEBOUNCE
For the Supply/Open case the wetting current into the sense
input is simply the current sunk by the effective 30kΩ to
GND. For VSENSE = 28V, IWET is 1mA. See Figure 2.
GND/OPEN SENSING
For GND/Open sensing, the CRn bit is set to 1. Referring to
the Block Diagram, Figure 1, this selection will connect a
12kΩ pull-up resistance through a diode to VDD. This
resistance gives extra noise immunity for detecting the open
state while providing contact wetting current. Open and
Closed states are detected according to the threshold levels
GLO and GHI programmed into the DAC Threshold Register,
see Figures 14 - 17 for thresholds. When the SENSE input
exceeds GHI, the output of the sensor goes high. The output
of the sensor remains high until a voltage of less than GLO is
detected at the SENSE input, representing a valid Ground
state and causing the sensor output to go low. The Sensor
will maintain a Ground detect state until the SENSE input
becomes greater than GHI. The difference GHI - GLO
represents the hysteresis which improves noise immunity
and reduces output chattering.
WETTING CURRENT
In GND/Open mode a current is sourced from the SENSE pin
when it is grounded and VDD is powered, see Figure 3.
This current called the “wetting current” serves to provide
current through switches or relay contacts to prevent dry
contacts and improve switch contact reliability.
BUILT-IN TEST
When the input DBNC is high, a debounce circuit on the
sensor outputs is enabled (see Figure 1). The comparator
outputs are sampled every 60ms, the state of the sensor
register bit is changed only when two consecutive samples
are identical. When debounce is enabled there will be
approximately 60ms delay before the sense data register is
updated.
DAC THRESHOLD REGISTER
The 24-bits [T24:1] in the DAC Register program the sensor
threshold levels for the eight discrete sensors. There are four
6 bit DACs:
GL5:0 GND/Open Low Threshold
GH5:0 GND/Open High Threshold
VL5:0 Supply/Open Low Threshold
VH5:0 Supply/Open High Threshold
The thresholds are programmed according to the two
formula below, for GND/Open and Supply/Open modes
respecitvely:
Vthresh(G/O) = VDD x (0.126 + D/91.6) Volts
Vthresh(S/O) = VDD x (0.144 + D/98.9) Volts
D is a value (0 to 63) programmed into the DAC
For further details see example DAC threshold
programming on page 12.
MSB
LSB
T24 T23 T22 T21 T20 T19 T18 T17 T16 T15 T14 T13
Writing a high in Control Register bit 9 puts the HI-8429 into
the Built-In Test (BIT) mode. In this mode setting a CRn bit
high for a particular sensor forces that comparator input
high. A zero in CRn forces the comparator input low. To
verify correct operation, the user must read from the Data
Register and compare this with the value written to CR1-8.
First Bit shifted out of SO
MSB
LSB
T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1
NOTE: Certain flight applications require periodic sensor
testing during flight. To ensure seamless transition between
BIT mode and normal operation mode, the following steps
should be followed:
1) The host should read and record the Configuration
Register value for normal mode operation.
2) The host should read and record the last value of
the Data Register before enabling BIT mode
(CR9 = 1).
3) Following test completion, but while still in BIT
Last Bit shifted out of SO
HOLT INTEGRATED CIRCUITS
5
5 Page 
HI-8429
FUNCTIONAL DESCRIPTION (cont.)
LIGHTNING PROTECTION
All SENSEn inputs are protected to RTCA/DO-160G, Section 22, Categories A3 and B3, Waveforms 3, 4, 5A, 5B with no
external components. Table 3 and Figure 13 give values and waveforms. Higher levels of lightning protection can be
implemented using a series resistor and a TVS, see Application Note AN-305 for recommendations.
Level
3
3/3
Voc (V) / Isc (A)
600/24
Waveforms
4/1 5A/5A
Voc (V) / Isc (A) Voc (V) / Isc (A)
300/60
300/300
5B/5B
Voc (V) / Isc (A)
300/300
Table 3. Waveform Peak Amplitudes
V/I (%)
Peak
1.0
0.5
0.0
Voltage/Current Waveform 3 V (%)
1.0 Peak
50%
0.8
0.5
Voltage Waveform 4
50%
-0.5 0.3
-1.0 0.0
t
1us/div.
T1
t
T2 T1 = 6.4µs +/-20%
T2 = 69µs +/-20%
I/V (%)
Current/Voltage Waveform 5A I/V (%) Current/Voltage Waveform 5B
1.0 Peak
1.0 Peak
0.8 0.8
50%
0.5 0.5
0.3 0.3
50%
0.0 T1
t T2
T1 = 40µs +/-20%
T2 = 120µs +/-20%
0.0
T1
Figure 13. Lightning Waveforms
HOLT INTEGRATED CIRCUITS
11
t
T2 T1 = 50µs +/-20%
T2 = 500µs +/-20%
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet HI-8429.PDF ] | |
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