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PDF AD9520-5 Data sheet ( Hoja de datos )
| Número de pieza | AD9520-5 | |
| Descripción | 12 LVPECL/24 CMOS Output Clock Generator | |
| Fabricantes | Analog Devices | |
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Data Sheet
12 LVPECL/24 CMOS Output
Clock Generator
AD9520-5
FEATURES
Low phase noise, phase-locked loop (PLL)
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Automatic/ manual reference holdover and reference
switchover modes, with revertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 outputs shares a 1-to-32 divider with
phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs < 16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual output synchronization available
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-51 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with
an on-chip PLL that can be used with an external VCO.
The AD9520-5 serial interface supports both SPI and I²C ports.
An in-package EEPROM, which can be programmed through the
serial interface, can store user-defined register settings for
power-up and chip reset.
FUNCTIONAL BLOCK DIAGRAM
CP
REFIN
REFIN
CLK
CLK
REF1
STATUS
MONITOR
REF2
DIVIDER
AND MUXES
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
ZERO
DELAY
LVPECL/
CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
SPI/I2C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9520-5
Figure 1.
The AD9520-5 features 12 LVPECL outputs in four groups. Any
of the 1.6 GHz LVPECL outputs can be reconfigured as two
250 MHz CMOS outputs. If an application requires LVDS
drivers instead of LVPECL drivers, refer to the AD9522-5.
Each group of three outputs has a divider that allows both the
divide ratio (from 1 to 32) and the phase offset or coarse time
delay to be set.
The AD9520-5 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage of up to 5.5 V. A separate output driver power
supply can be from 2.375 V to 3.465 V.
The AD9520-5 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-5 is used, it refers to that specific member of the
AD9520 family.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Reference Input Clock Doubler Frequency
Antibacklash Pulse Width
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. VCP
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL N DIVIDER DELAY
000
001
010
011
100
101
110
111
PLL R DIVIDER DELAY
000
001
010
011
100
101
110
111
AD9520-5
Min Typ Max Unit Test Conditions/Comments
0.004
1.3
2.9
6.0
100
45
50
4.8
0.60
2.5
2.7 10
1
1
1.5
2
MHz Antibacklash pulse width = 1.3 ns
MHz Antibacklash pulse width = 2.9 ns
MHz
ns Register 0x017[1:0] = 01b
ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
ns Register 0x017[1:0] = 10b
CPV is the CP pin voltage; VCP is the charge pump
power supply voltage (VCP pin)
Programmable
mA With CPRSET = 5.1 kΩ; higher ICP is possible by
changing CPRSET
mA With CPRSET = 5.1 kΩ; lower ICP is possible by
changing CPRSET
% CPV = VCP/2
kΩ
nA
% 0.5 V < CPV< VCP − 0.5 V; CPVis the CP pin voltage;
VCP is the charge pump power supply voltage
(VCP pin)
% 0.5 V < CPV < VCP − 0.5 V
% CPV = VCP /2
300 MHz
600 MHz
900 MHz
200 MHz
1000 MHz
2400 MHz
3000 MHz
3000 MHz
300 MHz A, B counter input frequency (prescaler input
frequency divided by P)
Register 0x019[2:0]; see Table 48
Off
385 ps
486 ps
623 ps
730 ps
852 ps
976 ps
1101
ps
Register 0x019[5:3]; see Table 48
Off
365 ps
486 ps
608 ps
730 ps
852 ps
976 ps
1101
ps
Rev. B | Page 5 of 74
5 Page 
Data Sheet
AD9520-5
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 7.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min Typ Max Unit
54 fs rms
77 fs rms
109 fs rms
79 fs rms
114 fs rms
163 fs rms
124 fs rms
176 fs rms
259 fs rms
Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R DIV = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 8.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
CLK = 622.08 MHz
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
CLK = 1000 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 10
CLK = 500 MHz
Any LVPECL Output = 100 MHz
Divide Ratio = 5
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 200 MHz
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min Typ Max Unit Test Conditions/Comments
Distribution section only; does not include the PLL;
measured at rising edge of the clock signal
46 fs rms Integration bandwidth = 12 kHz to 20 MHz
64 fs rms Integration bandwidth = 12 kHz to 20 MHz
223 fs rms Calculated from SNR of ADC method
Broadband jitter
209 fs rms Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include the PLL
325 fs rms Calculated from SNR of ADC method
Broadband jitter
Rev. B | Page 11 of 74
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9520-5.PDF ] | |
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