PDF AD9520-3 Data sheet ( Hoja de datos )

Número de pieza	AD9520-3
Descripción	12 LVPECL/24 CMOS Output Clock Generator
Fabricantes	Analog Devices
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Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9520-3 FEATURES Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.72 GHz to 2.25 GHz Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVDS, or LVPECL references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Automatic/manual reference holdover and reference switchover modes, with revertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 1.6 GHz LVPECL outputs divided into 4 groups Each group of 3 outputs shares a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs < 16 ps Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz) Automatic synchronization of all outputs on power-up Manual output synchronization available SPI- and I²C-compatible serial control port 64-lead LFCSP Nonvolatile EEPROM stores configuration settings APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures GENERAL DESCRIPTION The AD9520-31 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. FUNCTIONAL BLOCK DIAGRAM CP LF OPTIONAL REFIN REFIN CLK REF1 REF2 STATUS MONITOR VCO DIVIDER AND MUXES DIV/Φ DIV/Φ DIV/Φ DIV/Φ ZERO DELAY LVPECL/ CMOS OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 SPI/I2C CONTROL PORT AND EEPROM DIGITAL LOGIC AD9520 Figure 1. The AD9520-3 serial interface supports both SPI and I²C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset. The features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522-3. Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set. The is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V. The AD9520-3 is specified for operation over the standard industrial range of −40°C to +85°C. 1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-3 is used, it refers to that specific member of the AD9520 family. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD9520-3 Parameter Min Typ Max Unit Test Conditions/Comments Crystal Oscillator Crystal Resonator Frequency Range 16.62 33.33 MHz Maximum Crystal Motional Resistance 30 Ω PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency 100 MHz Antibacklash pulse width = 1.3 ns 45 MHz Antibacklash pulse width = 2.9 ns Reference Input Clock Doubler Frequency 0.004 50 MHz Antibacklash Pulse Width 1.3 ns Register 0x017[1:0] = 01b 2.9 ns Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b 6.0 ns Register 0x017[1:0] = 10b CHARGE PUMP (CP) CPV is the CP pin voltage; VCP is the charge pump power supply voltage (VCP pin) ICP Sink/Source High Value Low Value Programmable 4.8 mA With CPRSET = 5.1 kΩ; higher ICP is possible by changing CPRSET 0.60 mA With CPRSET = 5.1 kΩ; lower ICP is possible by changing CPRSET Absolute Accuracy 2.5 % CPV = VCP/2 CPRSET Range 2.7 10 kΩ ICP High Impedance Mode Leakage 1 nA Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature 1 % 0.5 V < CPV < VCP − 0.5 V; CPV is the CP pin voltage; VCP is the charge pump power supply voltage (VCP pin) 1.5 % 0.5 V < CPV < VCP − 0.5 V 2 % CPV = VCP/2 PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD 300 MHz P = 2 FD 600 MHz P = 3 FD 900 MHz P = 2 DM (2/3) 200 MHz P = 4 DM (4/5) 1000 MHz P = 8 DM (8/9) 2400 MHz P = 16 DM (16/17) 3000 MHz P = 32 DM (32/33) 3000 MHz Prescaler Output Frequency 300 MHz A, B counter input frequency (prescaler input frequency divided by P) PLL N DIVIDER DELAY Register 0x019[2:0]; see Table 54 000 Off 001 385 ps 010 486 ps 011 623 ps 100 730 ps 101 852 ps 110 976 ps 111 1101 ps PLL R DIVIDER DELAY Register 0x019[5:3]; see Table 54 000 Off 001 365 ps 010 486 ps 011 608 ps 100 730 ps 101 852 ps 110 976 ps 111 1101 ps Rev. B \| Page 5 of 80 5 Page Data Sheet AD9520-3 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE VCO = 2.25 GHz; Output = 2.25 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset VCO = 2 GHz; Output = 2 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset VCO = 1.75 GHz; Output = 1.75 GHz 1 kHz Offset 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset Min Typ Max Unit Test Conditions/Comments Internal VCO; direct-to-LVPECL output and for loop bandwidths < 1 kHz −50 −82 −107 −126 −140 −146 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −55 −85 −110 −129 −142 −147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −59 −89 −114 −132 −143 −147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R divider = 1 VCO = 1.966 GHz; LVPECL = 245.76 MHz; PLL LBW = 55 kHz 135 fs rms Integration BW = 200 kHz to 10 MHz 308 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.966 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz 129 fs rms Integration BW = 200 kHz to 10 MHz 293 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.966 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz 163 fs rms Integration BW = 200 kHz to 10 MHz 323 fs rms Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R divider = 162 VCO = 1.866 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.9 kHz 377 fs rms Integration BW = 12 kHz to 20 MHz VCO = 1.966 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.2 kHz 386 fs rms Integration BW = 12 kHz to 20 MHz Rev. B \| Page 11 of 80 11 Page

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