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AD9520-0 の電気的特性と機能

AD9520-0のメーカーはAnalog Devicesです、この部品の機能は「12 LVPECL/24 CMOS Output Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 AD9520-0
部品説明 12 LVPECL/24 CMOS Output Clock Generator
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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AD9520-0 Datasheet, AD9520-0 PDF,ピン配置, 機能
Data Sheet
12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2.8 GHz VCO
AD9520-0
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.53 GHz to 2.95 GHz
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVDS, or LVPECL references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Automatic/manual reference holdover and reference
switchover modes, with revertive switching
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 1.6 GHz LVPECL outputs divided into 4 groups
Each group of 3 outputs shares a 1-to-32 divider with
phase delay
Additive output jitter as low as 225 fs rms
Channel-to-channel skew grouped outputs < 16 ps
Each LVPECL output can be configured as 2 CMOS outputs
(for fOUT ≤ 250 MHz)
Automatic synchronization of all outputs on power-up
Manual output synchronization available
SPI- and I²C-compatible serial control port
64-lead LFCSP
Nonvolatile EEPROM stores configuration settings
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9520-01 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz
to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
FUNCTIONAL BLOCK DIAGRAM
CP LF
OPTIONAL
REFIN
REFIN
CLK
REF1
REF2
STATUS
MONITOR
VCO
DIVIDER
AND MUXES
DIV/Φ
DIV/Φ
DIV/Φ
DIV/Φ
ZERO
DELAY
LVPECL/
CMOS
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
SPI/I2C CONTROL
PORT AND
EEPROM
DIGITAL LOGIC
AD9520
Figure 1.
The AD9520-0 serial interface supports both SPI and I²C ports.
An in-package EEPROM, which can be programmed through the
serial interface, can store user-defined register settings for
power-up and chip reset.
The AD9520-0 features 12 LVPECL outputs in four groups. Any
of the 1.6 GHz LVPECL outputs can be reconfigured as two
250 MHz CMOS outputs. If an application requires LVDS
drivers instead of LVPECL drivers, refer to the AD9522-0.
Each group of three outputs has a divider that allows both the
divide ratio (from 1 to 32) and the phase offset or coarse time
delay to be set.
The AD9520-0 is available in a 64-lead LFCSP and can be operated
from a single 3.3 V supply. The external VCO can have an
operating voltage of up to 5.5 V. A separate output driver power
supply can be from 2.375 V to 3.465 V.
The AD9520-0 is specified for operation over the standard
industrial range of −40°C to +85°C.
1 AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-0 is used, it refers to that specific member of the
AD9520 family.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





AD9520-0 pdf, ピン配列
Data Sheet
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changed AD9520 to AD9520-0 .................................. Throughout
Change to PD Power-Down, Maximum Sleep Parameter,
Table 18.............................................................................................16
Updated Outline Dimensions........................................................80
8/2013—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and
General Description Section............................................................1
Changes to Table 2 ............................................................................4
Changes to Input Frequency Parameter; Change to Input
Sensitivity, Differential Parameter Test Conditions/Comments,
Table 3 .................................................................................................7
Change to Output Differential Voltage, VOD Parameter Test
Conditions/Comments; Added Source Current and Sink
Current Parameters, Table 4 ............................................................7
Reordered Figure 2 to Figure 4........................................................9
Change to Reset Timing, Pulse Width Low Parameter, Table 15...15
Change to PLL Locked; One LVPECL Output Enabled
Parameter, fOUT Value in Test Conditions/Comments, Table 18 ..16
Change to Junction Temperature, Table 19; Reformatted
Table 19 .....................................................................................................17
Change to Pin 4, Pin 10, and Pin 22 Descriptions, Table 21 .....18
Deleted Figure 13, Renumbered Sequentially .............................22
Reordered Figure 31 and Figure 32; Moved Figure 34 and
Figure 35 to PLL External Loop Filter Section, Page 35;
Added Figure 33, Renumbered Sequentially ...............................25
Change to Mode 0—Internal VCO and Clock Distribution
Section ..............................................................................................28
Change to Configuration of the PLL Section; Changes to
Charge Pump (CP) Section............................................................34
Changes to On-Chip VCO Section and PLL External Loop
Filter Section; Added Figure 40; Moved Figure 41 and Figure 42
from Typical Performance Characteristics Section to PLL
External Loop Filter Section; Changes to PLL Reference
Inputs Section ..................................................................................35
Changes to Reference Switchover Section ...................................36
Change to Prescaler Section and A and B Counters Section;
Changes to Table 29 ........................................................................37
Changes to Current Source Digital Lock Detect (CSDLD)
Section ..............................................................................................38
AD9520-0
Changes to Frequency Status Monitors Section and VCO
Calibration Section .........................................................................41
Added Table 31, Renumbered Sequentially; Change to
Internal Zero Delay Mode Section ...............................................42
Changes to External Zero Delay Mode Section ..........................43
Change to Clock Frequency Division Section; Added Channel
Divider Maximum Frequency Section .........................................45
Reformatted Table 36 to Table 39..................................................46
Change to Phase Offset or Coarse Time Delay Section.............47
Change to LVPECL Output Drivers Section; Changes to CMOS
Output Drivers Section ..................................................................49
Changes to Soft Reset via the Serial Port Section and Soft
Reset to Settings in EEPROM When EEPROM Pin = 0b
via the Serial Port Section ..............................................................50
Change to Pin Descriptions Section, SPI Mode Operation
Section, and Write Section.............................................................54
Changes to SPI Instruction Word (16 Bits) Section ...................55
Changes to EEPROM Operations Section, Writing to the
EEPROM Section, and Reading from the EEPROM Section ...58
Changes to Programming the EEPROM Buffer Segment
Section and Register Section Definition Group Section;
Added Operational Codes Section Heading ...............................59
Changes to Table 50 ........................................................................61
Added Unused Bits to Register Map Descriptions Section;
Changes to Address 0x000, Bit 5, and Added Address 0x003,
Table 51; Changes to Address 0x000, Bit 5, and Added
Address 0x003, Table 52 .................................................................64
Changes to Address 0x017, Table 54 ............................................66
Changes to Address 0x018, Bit 4 and Bits[2:1], Table 54...........67
Changes to Address 0x01B, Bits[4:0], Table 54 ...........................69
Changes to Address 0x191, Bit 5, and Address 0x194, Bit 5,
Table 56 .............................................................................................72
Changes to Address 0x197, Bit 5, Table 56 ..................................73
Changes to Address 0x19A, Bit 5, Table 56 .................................74
Changes to Table 60 ........................................................................75
Changes to Address 0xB02, Bit 0, and Address 0xB03, Bit 0,
Table 61.............................................................................................76
Change to Frequency Planning Using the AD9520 Section .....77
Added LVPECL Y-Termination and Far-End Thevenin
Termination Headings; Changes to CMOS Clock Distribution
Section .......................................................................................................78
9/2008—Revision 0: Initial Version
Rev. B | Page 3 of 80


3Pages


AD9520-0 電子部品, 半導体
AD9520-0
Data Sheet
Parameter
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVPECL Clock Output Pins)
in Internal Zero Delay Mode
Phase Offset (REF-to-LVPECL Clock Output Pins)
in Internal Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins)
in External Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins)
in External Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector2
Min
560
−320
140
−460
Typ
1060
+50
630
−20
Max
1310
+240
870
+200
500 kHz PFD Frequency
1 MHz PFD Frequency
10 MHz PFD Frequency
50 MHz PFD Frequency
PLL Figure of Merit (FOM)
−165
−162
−152
−144
−222
PLL DIGITAL LOCK DETECT WINDOW3
Lock Threshold (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)3
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
3.5
7.5
3.5
7
15
11
Unit Test Conditions/Comments
REF refers to REFIN (REF1)/REFIN (REF2)
ps When N delay and R delay are bypassed
ps When N delay setting = 110b, and R delay is bypassed
ps When N delay and R delay are bypassed
ps When N delay setting = 011b, and R delay is bypassed
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ns
ns
ns
ns
ns
ns
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the
value of the N divider)
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure
of merit decreases with decreasing slew rate; see
Figure 12
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings; the
lock detect threshold varies linearly with the value of
the CPRSET resistor
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from unlock to lock)
Register 0x017[1:0] = 00b, 01b,11b;
Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from lock to unlock)
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 In-band means within the LBW of the PLL.
3 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. B | Page 6 of 80

6 Page



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