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PDF AD9289 Data sheet ( Hoja de datos )
| Número de pieza | AD9289 | |
| Descripción | Serial LVDS 3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Four ADCs in one package
Serial LVDS digital output data rates to 520 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 48 dBc (to Nyquist)
Excellent linearity
DNL = ±0.2 LSB (typical)
INL = ±0.25 LSB (typical)
300 MHz full power analog bandwidth
Power dissipation = 112 mW/channel at 65 MSPS
1 Vp-p to 2 Vp-p input voltage range
3.0 V supply operation
Power-down mode
Digital test pattern enable for timing alignments
APPLICATIONS
Tape drives
Medical imaging
PRODUCT DESCRIPTION
The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital conver-
ter (ADC) with an on-chip sample-and-hold circuit that is
designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance where a small
package size is critical.
The ADC requires a single, 3 V power supply and an LVDS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported. The ADC typically consumes 7 mW when enabled.
Fabricated on an advanced CMOS process, the AD9289 is
available in a 64-ball mini-BGA package (64-BGA). It is
specified over the industrial temperature range of –40°C
to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Quad 8-Bit, 65 MSPS,
Serial LVDS 3 V A/D Converter
AD9289
FUNCTIONAL BLOCK DIAGRAM
AVDD
DFS PDWN DTP
DRVDD DRGND
VIN+A
VIN–A
AD9289
SHA
PIPELINE 8 SERIAL
ADC
LVDS
D1+A
D1–A
VIN+B
VIN–B
SHA
PIPELINE 8 SERIAL
ADC
LVDS
D1+B
D1–B
VIN+C
VIN–C
SHA
PIPELINE 8 SERIAL
ADC
LVDS
D1+C
D1–C
VIN+D
VIN–D
SHA
PIPELINE 8 SERIAL
ADC
LVDS
D1+D
D1–D
VREF
SENSE
REFT_A
REFB_A
REFT_B
REFB_B
REF
SELECT
0.5V
DATA RATE
MULTIPLIER
SHARED_REF AGND LVDSBIAS CML CLK+ CLK–
LOCK
FCO+
FCO–
DCO+
DCO–
Figure 1.
PRODUCT HIGHLIGHTS
1. Four ADCs are contained in a small, space-saving package.
2. A data clock out (DCO) is provided, which operates up to
260 MHz and supports double-data rate operation (DDR).
3. The outputs of each ADC are serialized LVDS with data
rates up to 520 Mbps (8 bits × 65 MSPS).
4. The AD9289 operates from a single 3.0 V power supply.
5. The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9289
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
SIGNAL-TO-NOISE RATIO (SINAD)
EFFECTIVE NUMBER OF BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second or Third)
WORST OTHER (Excluding Second or Third)
TWO TONE INTERMOD DISTORTION (IMD)
AIN1 and AIN2 = –7.0 dBFS
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 35 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 35 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 35 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 35 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 35 MHz
fIN = 2.4 MHz
fIN = 10.3 MHz
fIN = 35 MHz
fIN1 = 15 MHz
fIN2 = 16 MHz
Temperature
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
Full
25°C
Full
25°C
Test Level
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
V
Min
47.7
46.7
47.6
46.2
7.6
7.4
61.0
54.0
Typ
49.0
48.5
48.0
48.9
48.4
47.5
7.8
7.7
7.6
70.0
68.0
65.0
–75.0
–70.0
–65.0
–70.0
–68.0
–65.0
–72.0
Max
–61.0
–54.0
–61.0
–57.5
Unit
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
CLOCK INPUTS1 (CLK+, CLK–)
Logic Compliance
Differential Input Voltage
High Level Input Current
Low Level Input Current
Input Common-Mode Voltage
Input Resistance
Input Capacitance
LOGIC INPUTS (DFS, PDWN, SHARED_REF)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUTS (LOCK)
Logic 1 Voltage
Logic 0 Voltage
DIGITAL OUTPUTS (D1+, D1–)
Logic Compliance
Differential Output Voltage
Output Offset Voltage
Output Coding
Temperature
Full
Full
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Test Level
IV
VI
VI
IV
V
V
IV
IV
V
V
IV
IV
VI
VI
VI
Min Typ Max
LVDS
250
1.125
350 450
30 75
30 75
1.25 1.375
100
2
2.0
0.8
30
4
2.45
0.05
LVDS
260
1.15
350 440
1.25 1.35
Twos complement or binary
Unit
mV p-p
µA
µA
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
1 Clock inputs are LVDS-compatible. They require external dc bias and cannot be ac-coupled.
Rev. 0 | Page 4 of 32
5 Page 
AD9289
75
60 70dB REFERENCE LINE
50 1V p-p, SFDR (dBc)
2V p-p, SNR (dB)
40
30 1V p-p, SNR (dB)
20
10 2V p-p, SFDR (dBc)
0
–40 –35
–30 –25 –20 –15 –10
ANALOG INPUT LEVEL (dBFS)
–5
0
Figure 15. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS,
fIN = 2.4 MHz
75
60 70dB REFERENCE LINE
50 1V p-p, SFDR (dBc)
2V p-p, SNR (dB)
40
30 1V p-p, SNR (dB)
20
10 2V p-p, SFDR (dBc)
0
–40 –35
–30 –25 –20 –15 –10
ANALOG INPUT LEVEL (dBFS)
–5
0
Figure 16. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS,
fIN = 10.3 MHz
75
60 70dB REFERENCE LINE
50 1V p-p, SFDR (dBc)
2V p-p, SNR (dB)
40
30 1V p-p, SNR (dB)
20
10 2V p-p, SFDR (dBc)
0
–40 –35
–30 –25 –20 –15 –10
ANALOG INPUT LEVEL (dBFS)
–5
0
Figure 17. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS,
fIN = 35 MHz
75
70
SFDR (dBc)
65
60
55
50
45
0.1
SNR (dB)
1 10
FREQUENCY (MHz)
Figure 18. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz
100
0
AIN1 AND AIN2 = –7.0dBFS
SFDR = 69.9dBc
IMD2 = 74.9dBc
–20 IMD3 = 72.9dBc
–40
–60
–80
–100
0.0 4.1 8.1 12.2 16.3 20.3 24.4 28.4 32.5
FREQUENCY (MHz)
Figure 19. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 65 MSPS
80
70
60
70dB REFERENCE LINE
50
40
30 SFDR (dBc)
20
10
0
–40 –35
–30 –25 –20 –15 –10
ANALOG INPUT LEVEL (dBFS)
–5
0
Figure 20. Two-Tone SFDR vs. Analog Input Level with fIN1 = 15 MHz and
fIN2 = 16 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9289.PDF ] | |
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