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ADF4117 の電気的特性と機能

ADF4117のメーカーはAnalog Devicesです、この部品の機能は「RF PLL Frequency Synthesizers」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADF4117
部品説明 RF PLL Frequency Synthesizers
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADF4117 Datasheet, ADF4117 PDF,ピン配置, 機能
RF PLL Frequency Synthesizers
ADF4116/ADF4117/ADF4118
FEATURES
GENERAL DESCRIPTION
ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz
2.7 V to 5.5 V power supply
Separate VP allows extended tuning voltage in 3 V systems
Y Grade: −40°C to +125°C
Dual-modulus prescaler
ADF4116: 8/9
ADF4117/ADF4118: 32/33
3-wire serial interface
Digital lock detect
Power-down mode
Fastlock mode
The ADF411x family of frequency synthesizers can be used to
implement local oscillators (LO) in the upconversion and
downconversion sections of wireless receivers and transmitters.
They consist of a low noise digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, programmable A and B counters, and a dual-modulus
prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in
conjunction with the dual-modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R counter) allows selectable REFIN frequencies
at the PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO).
APPLICATIONS
All of the on-chip registers are controlled via a simple 3-wire
Base stations for wireless radio
(GSM, PCS, DCS, CDMA, WCDMA)
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
Wireless handsets
(GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
ADF4116/ADF4117/ADF4118
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
14-BIT
R COUNTER
14
R COUNTER
LATCH
21-BIT
INPUT REGISTER 19
FUNCTION
LATCH
SDOUT
FROM
FUNCTION LATCH
A, B COUNTER
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P + 1
LOAD
LOAD
5-BIT
A COUNTER
18
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AVDD
SDOUT
5
CE
AGND
DGND
Figure 1.
CHARGE
PUMP
MUX
HIGH Z
M3 M2 M1
FLO
SWITCH
CP
MUXOUT
FLO
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.

1 Page





ADF4117 pdf, ピン配列
ADF4116/ADF4117/ADF4118
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = TMIN to TMAX, unless otherwise
noted; dBm referred to 50 Ω.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Sensitivity
RF Input Frequency
ADF4116
ADF4117
ADF4118
Maximum Allowable Prescaler
Output Frequency3
REFIN CHARACTERISTICS
Reference Input Frequency
Reference Input Sensitivity4,5
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY5
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
Reference Input Current
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
B Version1
−15 to 0
−10 to 0
80 to 550
45 to 550
0.1 to 1.2
0.1 to 3.0
0.2 to 3.0
165
200
5 to 100
0.4 to AVDD
0.7 to AVDD
10
±100
55
1
250
2.5
3
1
3
2
2
0.8 × DVDD
0.2 × DVDD
±1
10
±100
DVDD − 0.4
0.4
Y Version2 Unit
Test Conditions/Comments
−10 to 0
−10 to 0
0.1 to 3.0
165
200
dBm min to max
dBm min to max
MHz min to max
MHz min to max
GHz min to max
GHz min to max
GHz min to max
MHz max
MHz max
AVDD = 3 V
AVDD = 5 V
See Figure 26 for input circuit
Input level = −8 dBm; for lower frequencies,
ensure slew rate (SR) > 36 V/μs
Input level = −10 dBm
Input level = −15 dBm
AVDD, DVDD = 3 V
AVDD, DVDD = 5 V
5 to 100
0.4 to AVDD
0.7 to AVDD
10
±100
55
MHz min to max
V p-p min to max
V p-p min to max
pF max
μA max
MHz max
For f < 5 MHz, ensure SR > 100 V/μs
AVDD = 3.3 V, biased at AVDD/2
For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/2
1 mA typ
250 μA typ
2.5 % typ
25 nA max
16 nA typ
3 % typ
2 % typ
2 % typ
0.8 × DVDD
0.2 × DVDD
±1
10
± 100
V min
V max
μA max
pF max
μA max
DVDD − 0.4 V min
0.4 V max
0.5 V ≤ VCP ≤ VP − 0.5
0.5 V ≤ VCP ≤ VP − 0.5
VCP = VP/2
IOH = 500 μA
IOL = 500 μA
Rev. D | Page 3 of 28


3Pages


ADF4117 電子部品, 半導体
ADF4116/ADF4117/ADF4118
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND1
VP to AVDD
Digital I/O Voltage to GND1
Analog I/O Voltage to GND1
REFIN, RFINA, RFINB to GND1
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Extended (Y Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
CMOS
Bipolar
Rating
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +5.5 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±320 mV
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
260°C
40 sec
6425
303
1 GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. D | Page 6 of 28

6 Page



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