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ADF4112 の電気的特性と機能

ADF4112のメーカーはAnalog Devicesです、この部品の機能は「RF PLL Frequency Synthesizers」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADF4112
部品説明 RF PLL Frequency Synthesizers
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADF4112 Datasheet, ADF4112 PDF,ピン配置, 機能
Data Sheet
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
FEATURES
GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz;
ADF4113: 4.0 GHz
2.7 V to 5.5 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler 8/9, 16/17, 32/33,
64/65
The ADF4110 family of frequency synthesizers can be used to
implement local oscillators in the upconversion and downcon-
version sections of wireless receivers and transmitters. They
consist of a low noise digital PFD (phase frequency detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents
(P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
Programmable antibacklash pulse width
with the dual-modulus prescaler (P/P + 1), implement an N
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete phase-locked loop (PLL) can be implemented
APPLICATIONS
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO).
WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications test equipment
Control of all the on-chip registers is via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP CPGND
RSET
REFERENCE
REFIN
CLK
DATA
LE
RFINA
RFINB
24-BIT
INPUT REGISTER 22
SDOUT
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
19
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
LOCK
DETECT
CURRENT CURRENT
SETTING 1 SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
FROM
FUNCTION
LATCH
13
N = BP + A
13-BIT
B COUNTER
PRESCALER
P/P +1
LOAD
LOAD
6-BIT
A COUNTER
AVDD
SDOUT
MUX
HIGH Z
M3 M2 M1
ADF4110/ADF4111
6 ADF4112/ADF4113
CE
AGND
DGND
Figure 1. Functional Block Diagram
CP
MUXOUT
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADF4112 pdf, ピン配列
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.
Table 1.
Parameter
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4110
ADF4111
ADF4112
ADF4112
ADF4113
Maximum Allowable Prescaler Output
Frequency2
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
RF Input Frequency
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
Maximum Allowable Prescaler Output
Frequency2
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR FREQUENCY4
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP 3-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
B Version B Chips1
−15/0
−15/0
Unit
dBm min/max
Test Conditions/Comments
See Figure 29 for input circuit.
80/550
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
165
80/550
50/550
0.08/1.2
0.2/3.0
0.1/3.0
0.2/3.7
165
MHz min/max
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
For lower frequencies, ensure slew rate
(SR) > 30 V/µs.
Input level = −10 dBm.
For lower frequencies, ensure SR > 30 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
Input level = −10 dBm.
Input level = −10 dBm. For lower frequencies,
ensure SR > 130 V/µs.
MHz max
−10/0
−10/0
dBm min/max
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
200
80/550
0.08/1.4
0.1/3.0
0.2/3.7
0.2/4.0
200
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 50 V/µs.
For lower frequencies, ensure SR > 75 V/µs.
For lower frequencies, ensure SR > 130 V/µs.
Input level = −5 dBm.
MHz max
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
5/104
0.4/AVDD
3.0/AVDD
10
±100
55
MHz min/max
V p-p min/max
V p-p min/max
pF max
µA max
MHz max
For f < 5 MHz, ensure SR > 100 V/µs.
AVDD = 3.3 V, biased at AVDD/2. See Note 3.
AVDD = 5 V, biased at AVDD/2. See Note 3.
5
625
2.5
2.7/10
1
2
1.5
2
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
Programmable (see Table 9).
With RSET = 4.7 kΩ.
With RSET = 4.7 kΩ.
See Table 9.
0.5 V ≤ VCP ≤ VP – 0.5 V.
0.5 V ≤ VCP ≤ VP – 0.5 V.
VCP = VP/2.
0.8 × DVDD
0.2 × DVDD
±1
10
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
IOH = 500 µA.
IOL = 500 µA.
Rev. F | Page 3 of 28


3Pages


ADF4112 電子部品, 半導体
ADF4110/ADF4111/ADF4112/ADF4113
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
LFCSP θJA Thermal Impedance
(Paddle Soldered)
LFCSP θJA Thermal Impedance
(Paddle Not Soldered)
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
1 GND = AGND = DGND = 0 V.
Rating
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
−0.3 V to +5.5 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
±320 mV
−40°C to +85°C
−65°C to +150°C
150°C
150.4°C/W
122°C/W
216°C/W
215°C
220°C
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 6 of 28

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共有リンク

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部品番号部品説明メーカ
ADF4110

RF PLL Frequency Synthesizers

Analog Devices
Analog Devices
ADF4111

RF PLL Frequency Synthesizers

Analog Devices
Analog Devices
ADF4112

RF PLL Frequency Synthesizers

Analog Devices
Analog Devices
ADF4113

RF PLL Frequency Synthesizers

Analog Devices
Analog Devices


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