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PDF KS0071B Data sheet ( Hoja de datos )
| Número de pieza | KS0071B | |
| Descripción | 32COM/60SEG DRIVER & CONTROLLER | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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KS0071B
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
INTRODUCTION
The KS0071B is a dot matrix LCD controller & driver LSI which is fabricated by low power CMOS technology,
designed to drive a split screen dot matrix LCD display of 1 line 24 characters or 2 line 24
characters with 57 dots format.
FEATURES
• Character type dot matrix single chip LCD controller & driver
• High voltage LCD driver 32 common and 60 segment signal output.
• Easy interface with a 4 bit or 8 bit MPU.
• Internal memory
-. Character generator ROM : 8400bits ( 240 characters for 57 dots )
-. Character generator RAM : 512 bits ( 8 patterns for 57 dots )
-. Display data RAM : 640 bits ( 808 bits for 80 characters )
• Maximum display characters
-. 1 line, 1/16 duty, 57 dots + cursor, 24 characters.
-. 2 line, 1/32 duty, 57 dots + cursor, 24 characters .
• A customer character pattern can be programmable by mask option.
•. The special character pattern can be programmable by character generator RAM directly.
• It is possible to read both character generator and display data RAM from MPU.
• Useful 11 code instruction set
• Automatic power on reset function
• On chip generation of LCD supply voltage from voltage doubler ( external supply also possible )
•.Voltage doubler generates about double from single power supply ( 5V)
• High contrast display can be performed though the simple power supply circuits.
• On chip oscillator requires external resistor ( external clock also possible )
• Power supply voltage: +5V10%, +3V20%
• Supply voltage for display: -5V
• Package outline: 118 TAB or bare chip available.
1 page  
KS0071B
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
PAD DESCRIPTION
PAD ( No.)
VDD ( 45 )
VSS ( 33 )
OSC1 ( 34 )
OSC2 ( 35 )
E (48)
R/W ( 47 )
NAME
Power Supply
Oscillator
Enable
Read / write
RS ( 46 )
Register select
DB0 ~ DB7
( 49 ~ 56 )
Data interface
VCI ( 44 )
C1 ( 42 )
C2 ( 43 )
Voltage doubler
output
Capacitor
V5OUT ( 41 )
V1,V2,V3,V4,V5
( 36 ~ 40 )
S1 ~ S44 ( 75~118)
S45 ~ S60 (1 ~ 16 )
C1 ~ C8 (74 ~ 67)
C9 ~ C16 (17~24)
C17 ~ C24 (66~59)
C25 ~ C32 (25~32)
T1(58),T2(57)
Voltage doubler
output
LCD supply
Voltage
Segment output
Common output
Test pin
I/O
Input
Input
output
Input
Input
Description
For logical circuit (+5V10%,+3V20%)
0V (GND)
OSC1 and OSC2 pin should be connected to
external Rf resistor for internal oscillator.
External clock can be input to OSC1.
Start enable signal to read or write the data
R/W signal input is used to select the
read/write mode
Interface
Power supply
Resistor or
external clock
MPU
MPU
High
Low
Read mode
Write mode
Input
Register select input.
High
Low
Data register
(for read and write)
Instruction register
(for write) busy flag,
address counter (for read)
MPU
Input/
output
Input
Input
Output
Input
Used for data transfer between the MPU
and KS0071B, These terminals are for data
bus with bidirectional three-state.
lower 4 bit (DB0 ~ DB3) are not used
during 4 bit operation
(DB7 can be used as a busy flag. )
Input terminal for voltage doubler.
(normally VCI=VDD)
Capacitor for voltage doubler connecting
terminal (+).
Capacitor for voltage doubler connecting
terminal(-).
Voltage doubler output terminal connected
to LCD supply voltage
Bias voltage level for LCD driving
Output Segment signal output for LCD driving
Output Common signal output for LCD driving
MPU
Power
supply
Capacitor
V5
Divide resistor
LCD
LCD
Input Maker testing terminal (normally open)
5 Page 
KS0071B
32COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD
CONTROL and DISPLAY COMMAND
Command RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display clear L L L L L L L L L H
Return home L L L L L L L L H X
Entry mode set L L L L L L L H I/D SH
Execution
time
fOSC=250KHz
1.64mS
1.64mS
40uS
Remark
Cursor move to first digit
I/D: Set cursor move direction
I/D H Increase
L Decrease
SH: Specifies shift of display
SH H Display is shifted
L Display is not shifted
Display on/off L L L L L L H D C B
40uS
Display
D H Display on
L Display off
Cursor
C H Cursor on
L Cursor off
Blinking
B H Blinking on
L Blinking off
Shift
L L L L L H S/C R/L X X
40uS
S/C H Display shift
L Cursor move
R/L H Right shift
L Left shift
Set
function
L L L L H DL N X X X
Set CG RAM L L L H CG RAM address
address
(corresponds to cursor address)
Set DD RAM L L H
address
DD RAM address
Read busy L
flag & address
H BF Address counter used for both DD
& CG RAM address
Write data
Read data
HL
HH
Write data
Read data
40uS
40uS
40uS
0uS
46uS
46uS
DL H 8 bits interface
L 4 bits interface
N H 2 line display
L 1line display
CG RAM data is sent and
received after this setting
DD RAM data is sent and
received after this setting
BF H Busy
L Ready
- Reads BF indication internal
operating performed
- Reads address counter contents
Write data into DD or CG RAM
Read data into DD or CG RAM
x : don’t care
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet KS0071B.PDF ] | |
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