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PDF RTL8326 Data sheet ( Hoja de datos )

Número de pieza RTL8326
Descripción 24-PORT 10/100M + 2-PORT 10/100/1000M ETHERNET SWITCH CONTROLLER
Fabricantes Realtek　
Logotipo Realtek Logotipo



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No Preview Available ! RTL8326 Hoja de datos, Descripción, Manual

RTL8326
24-PORT 10/100M + 2-PORT 10/100/1000M
ETHERNET SWITCH CONTROLLER WITH
EMBEDDED MEMORY
DATASHEET
Rev. 2.1
27 November 2003
Track ID: JATR-1076-21

1 page




RTL8326 pdf
RTL8326
Datasheet
7.29.1. SMI (MDC, MDIO) Interface ...............................................................................................................................51
7.29.2. PHY Register Indirect Access ...............................................................................................................................51
7.30. GENERAL PURPOSE I/O INTERFACE............................................................................................................................51
7.31. LED INTERFACES.......................................................................................................................................................51
7.32. PARALLEL LED INTERFACE........................................................................................................................................51
7.33. SERIAL LED INTERFACE ............................................................................................................................................52
7.33.1. Serial LED Display Panel Example (4 LEDs, Register 0x0005)..........................................................................53
7.33.2. Serial LED Shift Out Sequence Order ..................................................................................................................53
8. SERIAL EEPROM CONFIGURATION (24LC024) ......................................................................................................54
8.1. EEPROM CONFIGURATION VS. INTERNAL REGISTER MAPPING TABLE .....................................................................54
9. INTERNAL REGISTER DESCRIPTIONS.....................................................................................................................55
9.1. SYSTEM CONFIGURATION REGISTERS ........................................................................................................................55
9.2. SYSTEM STATUS REGISTERS.......................................................................................................................................56
9.3. MANAGEMENT CONFIGURATION REGISTERS..............................................................................................................56
9.4. ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER ...............................................................................................56
9.5. QUEUE CONTROL REGISTERS.....................................................................................................................................59
9.6. PHY ACCESS CONTROL REGISTER .............................................................................................................................59
9.7. PORT CONTROL REGISTERS........................................................................................................................................60
9.8. MIB COUNTER REGISTERS.........................................................................................................................................60
9.8.1. Port MIB Counter 1 Register (RX Counter) (32-bits) ..........................................................................................61
9.8.2. Port MIB Counter 2 Register (TX Counter) (32-bits)...........................................................................................62
9.8.3. Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)..............................................................................63
9.9. SYSTEM PARAMETER REGISTER (RESERVED) .............................................................................................................63
10. INTERNAL REGISTER SETTINGS...........................................................................................................................64
10.1. SYSTEM CONFIGURATION REGISTER ..........................................................................................................................64
10.1.1. 0x0000H: System Reset Control Register .............................................................................................................64
10.1.2. 0x0001H: Switch Parameter Register ..................................................................................................................65
10.1.3. 0x0002H: RX I/O PAD Delay Configuration........................................................................................................66
10.1.4. 0x0003H: TX I/O PAD Delay Configuration ........................................................................................................67
10.1.5. 0x0004H: General Purpose User Defined I/O Data Register ..............................................................................67
10.2. 0X0005H: LED DISPLAY CONFIGURATION ................................................................................................................68
10.3. SYSTEM STATUS REGISTER.........................................................................................................................................69
10.3.1. 0x0100H: Board Trapping Status Register...........................................................................................................69
10.3.2. 0x0101H: Loop Detect Status Register (32-Bit Register) .....................................................................................69
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller v
Track ID: JATR-1076-21 Rev.2.1

5 Page





RTL8326 arduino
RTL8326
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM........................................................................................................................................................14
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM ..................................................................................................................................15
FIGURE 3. PIN ASSIGNMENTS ......................................................................................................................................................16
FIGURE 4. 802.1Q VLAN TAG FRAME FORMAT..........................................................................................................................41
FIGURE 5. IPV4 FRAME FORMAT .................................................................................................................................................41
FIGURE 6. IPV6 FRAME FORMAT .................................................................................................................................................41
FIGURE 7. REALTEK REMOTE CONTROL PROTOCOL ....................................................................................................................43
FIGURE 8. HELLO/GET/SET/GET_REPLY PACKET FORMAT .........................................................................................................44
FIGURE 9. HELLO_REPLY PACKET FORMAT ................................................................................................................................45
FIGURE 10. LOOP DETECT PACKET FORMAT.................................................................................................................................46
FIGURE 11. REALTEK ECHO PROTOCOL FRAME ............................................................................................................................47
FIGURE 12. SERIAL CPU INTERFACE.............................................................................................................................................48
FIGURE 13. START AND STOP DEFINITION.....................................................................................................................................49
FIGURE 14. OUTPUT ACKNOWLEDGE (ACK) ................................................................................................................................49
FIGURE 15. SERIAL CPU 16-BIT READ/WRITE FORMAT ...............................................................................................................50
FIGURE 16. SERIAL CPU 32-BIT READ/WRITE FORMAT ...............................................................................................................50
FIGURE 17. SERIAL LED DISPLAY ................................................................................................................................................53
FIGURE 18. MDC/MDIO WRITE TIMING ......................................................................................................................................92
FIGURE 19. MDC/MDIO READ TIMING........................................................................................................................................92
FIGURE 20. MDC/MDIO RESET TIMING.......................................................................................................................................92
FIGURE 21. SMII TRANSMIT TIMING.............................................................................................................................................93
FIGURE 22. SMII RECEIVE TIMING ...............................................................................................................................................93
FIGURE 23. GMII TRANSMIT TIMING ............................................................................................................................................94
FIGURE 24. GMII RECEIVE TIMING...............................................................................................................................................94
FIGURE 25. MII TRANSMIT TIMING...............................................................................................................................................95
FIGURE 26. MII RECEIVE TIMING..................................................................................................................................................95
FIGURE 27. TBI TRANSMIT TIMING...............................................................................................................................................96
FIGURE 28. TBI RECEIVE TIMING .................................................................................................................................................96
FIGURE 29. CROSS-SECTION OF 208 PQFP ....................................................................................................................................97
24-Port + 2-Port 10/100/1000 Ethernet Switch Controller xi
Track ID: JATR-1076-21 Rev.2.1

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