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HI-6135 の電気的特性と機能

HI-6135のメーカーはHOLTICです、この部品の機能は「Compact Remote Terminal」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI-6135
部品説明 Compact Remote Terminal
メーカ HOLTIC
ロゴ HOLTIC ロゴ 




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HI-6135 Datasheet, HI-6135 PDF,ピン配置, 機能
November, 2016
MAMBATM: HI-6135
3.3V MIL-STD-1553 / MIL-STD-1760
Compact Remote Terminal with SPI Host Interface
GENERAL DESCRIPTION
PIN CONFIGURATION (TOP)
The 3.3V CMOS HI-6135 device is a member of
Holt’s MIL-STD-1553 MAMBATM family and provides a
complete Remote Terminal interface between a host
processor and MIL-STD-1553B bus. The terminal
communicates with the MIL-STD-1553 buses through an
on-chip dual bus transceiver and external transformers.
The user allocates 16K bytes of on-chip static RAM to
suit application requirements.
The HI-6135 communicates with the host via a 40 MHz
4-wire serial peripheral interface (SPI). Programmable
interrupts provide terminal status to the host processor.
Circular data buffers in RAM have interrupts for rollover
and programmable “level attained”.
The HI-6135 can be configured for automatic self-
initialization after reset. A dedicated SPI port reads
data from an external serial EEPROM to fully configure
registers and RAM and optionally start execution.
FEATURES
8K x 17-bit words internal static RAM with parity
Autonomous terminal operation requires minimal
host intervention.
40 MHz SPI Host Interface.
MIL-STD-1760 option sets Busy bit in Status
Word response during initialization.
World’s smallest RT solution, QFN package
measures just 6mm x 6mm.
16-bit time tag counter and independent clock
sources.
64-Word Interrupt Log Buffer queues the most
recent 32 interrupts. Hardware-assisted interrupt
decoding quickly identifies interrupt sources.
Built-in self-test for protocol logic, digital signal
paths and internal RAM.
Optional self-initialization at reset uses external
serial EEPROM.
±8kV ESD Protection (HBM, all pins).
Two temperature ranges: -40oC to +85oC, or
-55oC to +125oC with optional burn-in.
RoHS compliant and Tin / Lead options available.
MODE - 1
IRQ - 2
ACKIRQ - 3
MODE1760 - 4
READY - 5
VCC - 6
GND - 7
ACTIVE - 8
RTSSF - 9
AUTOEN - 10
TXINHA - 11
TXINHB - 12
HI-6135PCIF
HI-6135PCTF
HI-6135PCMF
36 - TTCLK
35 - ESCLK
34 - EECOPY
33 - ECS
32 - MOSI
31 - VCC
30 - GND
29 - MISO
28 - TESTB
27 - LOCK
26 - RTA4
25 - RTA3
48 - Pin Plastic 6mm x 6mm
Chip-Scale Package (QFN)
MODE - 1
IRQ - 2
ACKIRQ - 3
MODE1760 - 4
READY - 5
VCC - 6
GND - 7
ACTIVE - 8
RTSSF - 9
AUTOEN - 10
TXINHA - 11
TXINHB - 12
HI-6135PQIF
HI-6135PQTF
HI-6135PQMF
36 - TTCLK
35 - ESCLK
34 - EECOPY
33 - ECS
32 - MOSI
31 - VCC
30 - GND
29 - MISO
28 - TESTB
27 - LOCK
26 - RTA4
25 - RTA3
48 - Pin Plastic Quad Flat Pack (PQFP)
DS6135 Rev. C
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
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HI-6135 pdf, ピン配列
HI-6135
Table of Contents
1. BLOCK DIAGRAM............................................................................................ 10
2. FEATURE OVERVIEW .................................................................................... 11
2.1. Remote Terminal Operation....................................................................................... 11
2.2. Interrupts.................................................................................................................... 11
2.3. Reset and Initialization............................................................................................... 11
3. PIN DESCRIPTIONS........................................................................................ 12
4. MEMORY MAP.................................................................................................. 15
5. RAM STRUCTURES ........................................................................................ 16
5.1. Interrupt Log Data Buffer........................................................................................... 16
5.2. Command Illegalization Table.................................................................................... 16
5.3. Descriptor Table......................................................................................................... 16
5.4. Temporary Receive Buffers........................................................................................ 16
5.5. Message Data Buffers............................................................................................... 16
5.6. Storage for Mode Code Commands.......................................................................... 16
6. HARDWARE FEATURES ................................................................................. 17
6.1. Remote Terminal Address Inputs............................................................................... 17
6.2. Dual Transceivers for MIL-STD-1553 Bus................................................................. 17
6.3. Encoder and Decoders.............................................................................................. 17
6.4. Auto-Initialization Serial EEPROM Interface.............................................................. 17
6.5. Transmit Time-out Fail-Safe Counter......................................................................... 17
6.6. MIL-STD-1760 Mode................................................................................................. 17
7. REGISTER & MEMORY ADDRESSING........................................................... 18
8. REGISTER DEFINITIONS................................................................................ 18
9. REGISTERS...................................................................................................... 21
9.1. Master Configuration Register 1 (0x0000)................................................................. 21
9.2. Master Configuration Register 2 (0x004E)................................................................. 24
9.3. Master Status and Reset Register (0x0001) ............................................................. 26
9.4. Overview of Interrupts................................................................................................ 27
9.5. Hardware Interrupt Behavior...................................................................................... 28
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-6135 電子部品, 半導体
HI-6135
15. RESET AND INITIALIZATION......................................................................... 115
15.1. Hardware Master Reset and Optional Auto-Initialization......................................... 115
15.2. Initialization using EE2K Pin.................................................................................... 117
15.3. Memory Test Fail Address Register (0x0024)........................................................ 118
15.4. Remote Terminal Software Reset............................................................................ 119
15.5. MIL-STD-1760 Mode of Operation........................................................................... 120
16. SELF-TEST..................................................................................................... 121
16.1. Optional RAM Self-Test after Hardware Master Reset............................................ 121
16.2. Host-Directed Self-Test............................................................................................ 121
16.2.1. Self-Test Control Register (0x0028) .................................................................. 121
16.2.2. Loopback Test Transmit Data Register (0x001F)............................................... 125
16.2.3. Loopback Test Receive Data Register (0x0002)................................................ 125
16.2.4. RAM Self-Test Fail Address Register (0x001B).................................................. 125
16.2.5. Host-Directed RAM Self-Test................................................................................ 126
16.2.6. Host-Directed RT-Mode Loopback Testing (On-Line Analog or Off-Line Digital) .126
17. HOST SERIAL PERIPHERAL INTERFACE (SPI)........................................... 128
17.1. Serial Peripheral Interface (SPI) Basics .................................................................. 128
17.2. SPI Commands........................................................................................................ 129
17.3. Fast-Access Commands for Registers 0-15 ........................................................... 129
17.4. Fast-Access Write Commands for Registers 0-63 .................................................. 129
17.5. Indirect Addressing of RAM and Registers ............................................................. 129
17.6. Data Prefetch for SPI Read Cycles ......................................................................... 132
17.7. Special Purpose Commands .................................................................................. 132
17.8. RT Descriptor Table Prefetch Exceptions ............................................................... 134
18. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS .... 139
19. ELECTRICAL CHARACTERISTICS............................................................... 166
19.1. Absolute Maximum Ratings..................................................................................... 166
19.2. Recommended Operating Conditions...................................................................... 166
19.3. DC Electrical Characteristics................................................................................... 166
19.4. AC Electrical Characteristics ― Host Bus Interface (SPI) Timing............................ 168
20. MIL-STD-1553 BUS INTERFACE................................................................... 169
21. ORDERING INFORMATION........................................................................... 170
HOLT INTEGRATED CIRCUITS
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6 Page



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