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HI-3582 の電気的特性と機能

HI-3582のメーカーはHOLTICです、この部品の機能は「3.3V Terminal IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI-3582
部品説明 3.3V Terminal IC
メーカ HOLTIC
ロゴ HOLTIC ロゴ 




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HI-3582 Datasheet, HI-3582 PDF,ピン配置, 機能
August 2013
HI-3582, HI-3583
ARINC 429
3.3V Terminal IC
GENERAL DESCRIPTION
APPLICATIONS
The HI-3582/HI-3583 from Holt Integrated Circuits are
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-3582/HI-3583 design offers many enhancements to the
industry standard HI-8282 architecture. The device
provides two receivers each with label recognition, 32 by
32 FIFO, and analog line receiver. Up to 16 labels may be
programmed for each receiver. The independent transmit-
ter has a 32 X 32 FIFO and a built-in line driver. The status
of all three FIFOs can be monitored using the external
status pins, or by polling the HI-3582/HI-3583 status
register. Other new features include a programmable
option of data or parity in the 32nd bit, and the ability to
unscramble the 32 bit word. Also, versions are available
with different values of input resistance and output
resistance to allow users to more easily add external
lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3582/HI-3583 apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
Although the line driver shares a common substrate with
the receivers, the design of the physical isolation does not
allow parasitic crosstalk, and thereby achieves the same
isolation as common hybrid layouts.
FEATURES
ARINC specification 429 compatible
• 3.3V logic supply operation
• Dual receiver and transmitter interface
• Analog line driver and receivers connect
directly to ARINC bus
• Programmable label recognition
• On-chip 16 label memory for each receiver
• 32 x 32 FIFOs each receiver and transmitter
• Independent data rate selection for
Transmitter and each receiver
• Status register
• Data scramble control
• 32nd transmit bit can be data or parity
• Self test mode
• Low power
• Industrial & extended temperature ranges
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3582PCI
HI-3582PCT
HI-3582PCM
&
HI-3583PCI
HI-3583PCT
HI-3583PCM
48 - CWSTR
47 - ENTX
46 - N/C
45 - V+
44 - TXBOUT
43 - TXAOUT
42 - V-
41 - N/C
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package (QFN)
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3582PQI
HI-3582PQT
HI-3582PQM
&
HI-3583PQI
HI-3583PQT
HI-3583PQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
52 - Pin Plastic Quad Flat Pack (PQFP)
(DS3582 Rev. K)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13

1 Page





HI-3582 pdf, ピン配列
HI-3582, HI-3583
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3582/HI-3583 contain a 16-bit control register which is
used to configure the device. The control register bits CR0 - CR15
are loaded from BD00 - BD15 when CWSTR is pulsed low. The
control register contents are output on the databus when SEL = 1
and RSR is pulsed low. Each bit of the control register has the
following function:
CR
Bit
FUNCTION
CR0
Receiver 1
Data clock
Select
CR1 Label Memory
Read / Write
CR2
CR3
CR4
CR5
Enable Label
Recognition
(Receiver 1)
Enable Label
Recognition
(Receiver 2)
Enable
32nd bit
as parity
Self Test
CR6
Receiver 1
decoder
CR7
-
CR8
-
CR9
Receiver 2
Decoder
CR10
-
CR11
-
CR12
CR13
CR14
CR15
Invert
Transmitter
parity
Transmitter
data clock
select
Receiver 2
data clock
select
Data
format
STATE
DESCRIPTION
0 Data rate = CLK/10
1 Data rate = CLK/80
0 Normal operation
1 Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
0 Disable label recognition
1 Enable label recognition
0 Disable Label Recognition
1 Enable Label recognition
0 Transmitter 32nd bit is data
1 Transmitter 32nd bit is parity
0 The transmitter’s digital
outputs are internally connected
to the receiver logic inputs
1 Normal operation
0 Receiver 1 decoder disabled
1 ARINC bits 9 and 10 must match
CR7 and CR8
- If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
- If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
0 Receiver 2 decoder disabled
1 ARINC bits 9 and 10 must match
CR10 and CR11
- If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
- If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
0 Transmitter 32nd bit is Odd parity
1 Transmitter 32nd bit is Even parity
0 Data rate=CLK/10, O/P slope=1.5us
1 Data rate=CLK/80, O/P slope=10us
0 Data rate=CLK/10
1 Data rate=CLK/80
0 Scramble ARINC data
1 Unscramble ARINC data
STATUS REGISTER
The HI-3582/HI-3583 contain a 9-bit status register which can be
interrogated to determine the status of the ARINC receivers, data
FIFOs and transmitter. The contents of the status register are
output on BD00 - BD08 when the RSR pin is taken low and
SEL = 0. Unused bits are output as Zeros. The following table
defines the status register bits.
SR
Bit
FUNCTION
STATE
DESCRIPTION
SR0
Data ready
(Receiver 1)
0 Receiver 1 FIFO empty
1 Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
SR1 FIFO half full
(Receiver 1)
0 Receiver 1 FIFO holds less than 16
words
1 Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
SR2
FIFO full
(Receiver 1)
0 Receiver 1 FIFO not full
1 Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
SR3
Data ready
(Receiver 2)
0 Receiver 2 FIFO empty
1 Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
SR4 FIFO half full
(Receiver 2)
0 Receiver 2 FIFO holds less than 16
words
1 Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
SR5
FIFO full
(Receiver 2)
0 Receiver 2 FIFO not full
1 Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
SR6 Transmitter FIFO
empty
0
1
Transmitter FIFO not empty
Transmitter FIFO empty.
SR7 Transmitter FIFO
0
Transmitter FIFO not full
full
1 Transmitter FIFO full. FFT pin is the
inverse of this bit.
SR8 Transmitter FIFO
half full
0
Transmitter FIFO contains less than
16 words
1 Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-3582 電子部品, 半導体
HI-3582, HI-3583
FUNCTIONAL DESCRIPTION (cont.)
SEL
EN
MUX
CONTROL
TO PINS
32 TO 16 DRIVER
R/W
CONTROL
CONTROL
BITS
HF
FF
D/R
FIFO
LOAD
CONTROL
CONTROL
BIT
32 X 32
FIFO
/ LABEL /
DECODE
COMPARE
CONTROLBITS
CR0, CR14
CLOCK
OPTION
16 x 8
LABEL
MEMORY
EOS
32 BIT SHIFT REGISTER
DATA PARITY
CHECK
BIT CLOCK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
ONES
NULL
SHIFT REGISTER
SHIFT REGISTER
WORD GAP
WORD GAP
TIMER
BIT CLOCK
START
SEQUENCE
CONTROL
END
CLOCK
ZEROS
SHIFT REGISTER
ERROR
DETECTION
ERROR
CLOCK
FIGURE 2. RECEIVER BLOCK DIAGRAM
CLK
HOLT INTEGRATED CIRCUITS
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
HI-3582

3.3V Terminal IC

HOLTIC
HOLTIC
HI-3582A

3.3V Terminal IC

HOLTIC
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HI-3583

3.3V Terminal IC

HOLTIC
HOLTIC
HI-3583A

3.3V Terminal IC

HOLTIC
HOLTIC


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