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HI-3584A の電気的特性と機能

HI-3584AのメーカーはHOLTICです、この部品の機能は「ARINC 429 3.3V Serial Transmitter and Dual Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI-3584A
部品説明 ARINC 429 3.3V Serial Transmitter and Dual Receiver
メーカ HOLTIC
ロゴ HOLTIC ロゴ 




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HI-3584A Datasheet, HI-3584A PDF,ピン配置, 機能
July 2013
HI-3584A
ARINC 429 3.3V Serial Transmitter
and Dual Receiver with High-Speed Interface
GENERAL DESCRIPTION
The HI-3584A from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-3584A design offers a high-
speed host CPU interface compared with the earlier HI-
3584 product. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO. The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-3584A’s status
register.
Other features include a programmable option of data or
parity in the 32nd bit, and the ability to unscramble the 32 bit
word. Also, versions are available with different values of
input resistance to allow users to more easily add external
lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3584A applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
Additional interface circuitry such as the Holt HI-8570 or
HI-8571 is required to translate the transmitter’s 3.3 volt
logic outputs to ARINC 429 drive levels.
FEATURES
• ARINC specification 429 compatible
• 3.3V logic supply operation
• Dual receiver and transmitter interface
• Analog line receivers connect directly to ARINC bus
• Programmable label recognition
• On-chip 16 label memory for each receiver
• 32 x 32 FIFOs each receiver and transmitter
• Independent data rate selection for transmitter
and each receiver
• Status register
• Data scramble control
• 32nd transmit bit can be data or parity
• Self test mode
• Low power
• Industrial & Extended temperature ranges
APPLICATIONS
• Avionics data communication
• Serial to parallel conversion
• Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 13 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3584APCI
HI-3584APCT
&
HI-3584APCM
48 - CWSTR
47 - ENTX
46 - 429DO
45 - N/C
44 - N/C
43 - N/C
42 - N/C
41 - 429DO
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3584APQI
HI-3584APQT
&
HI-3584APQM
39 - N/C
38 - CWSTR
37 - ENTX
36 - N/C
35 - 429DO
34 - 429DO
33 - N/C
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
52 - Pin Plastic Quad Flat Pack (PQFP)
(DS3584A Rev. C)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13

1 Page





HI-3584A pdf, ピン配列
HI-3584A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-3584A contains a 16-bit control register which is used to
configure the device. The control register bits CR0 - CR15 are
loaded from BD00 - BD15 when CWSTR is pulsed low. The con-
trol register contents are output on the databus when SEL = 1 and
RSR is pulsed low. Each bit of the control register has the follow-
ing function:
STATUS REGISTER
The HI-3584A contains a 9-bit status register which can be interro-
gated to determine the status of the ARINC receivers, data FIFOs
and transmitter. The contents of the status register are output on
BD00 - BD08 when the RSR pin is taken low and SEL = 0. Unused
bits are output as zeros. The following table defines the status reg-
ister bits.
CR
Bit
FUNCTION
CR0
Receiver 1
Data clock
Select
CR1 Label Memory
Read / Write
CR2
CR3
CR4
CR5
Enable Label
Recognition
(Receiver 1)
Enable Label
Recognition
(Receiver 2)
Enable
32nd bit
as parity
Self Test
CR6
Receiver 1
decoder
CR7
-
CR8
-
CR9
Receiver 2
Decoder
CR10
-
CR11
-
CR12
CR13
CR14
CR15
Invert
Transmitter
parity
Transmitter
data clock
select
Receiver 2
data clock
select
Data
format
STATE
DESCRIPTION
0 Data rate = CLK/10
1 Data rate = CLK/80
0 Normal operation
1 Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
0 Disable label recognition
1 Enable label recognition
0 Disable Label Recognition
1 Enable Label recognition
0 Transmitter 32nd bit is data
1 Transmitter 32nd bit is parity
0 The 429DO and 429DO digital
outputs are internally connected
to the receiver logic inputs
1 Normal operation
0 Receiver 1 decoder disabled
1 ARINC bits 9 and 10 must match
CR7 and CR8
- If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
- If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
0 Receiver 2 decoder disabled
1 ARINC bits 9 and 10 must match
CR10 and CR11
- If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
- If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
0 Transmitter 32nd bit is Odd parity
1 Transmitter 32nd bit is Even parity
0 Data rate=CLK/10, O/P slope=1.5us
1 Data rate=CLK/80, O/P slope=10us
0 Data rate=CLK/10
1 Data rate=CLK/80
0 Scramble ARINC data
1 Unscramble ARINC data
SR
Bit
FUNCTION
STATE
DESCRIPTION
SR0
Data ready
(Receiver 1)
0 Receiver 1 FIFO empty
1 Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
SR1 FIFO half full
(Receiver 1)
0 Receiver 1 FIFO holds less than 16
words
1 Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
SR2
FIFO full
(Receiver 1)
0 Receiver 1 FIFO not full
1 Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
SR3
Data ready
(Receiver 2)
0 Receiver 2 FIFO empty
1 Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
SR4 FIFO half full
(Receiver 2)
0 Receiver 2 FIFO holds less than 16
words
1 Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
SR5
FIFO full
(Receiver 2)
0 Receiver 2 FIFO not full
1 Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
SR6 Transmitter FIFO
empty
0
1
Transmitter FIFO not empty
Transmitter FIFO empty.
SR7 Transmitter FIFO
0
Transmitter FIFO not full
full
1 Transmitter FIFO full. FFT pin is the
inverse of this bit.
SR8 Transmitter FIFO
half full
0
Transmitter FIFO contains less than
16 words
1 Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-3584A 電子部品, 半導体
HI-3584A
FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, then EOS
clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both)
will go low. The data flag for a receiver will remain low until both
ARINC bytes from that receiver are retrieved and the FIFO is
empty. This is accomplished by first activating EN with SEL, the
byte selector, low to retrieve the first byte and then activating EN
with SEL high to retrieve the second byte. EN1 retrieves data
from receiver 1 and EN2 retrieves data from receiver 2.
Up to 32 ARINC words may be loaded into each receiver’s FIFO.
The FF1 (FF2) pin will go low when the receiver 1 (2) FIFO is full.
Failure to retrieve data from a full FIFO will cause the next valid
ARINC word received to overwrite the existing data in FIFO
location 32. A FIFO half full flag HF1 (HF2) goes low if the FIFO
contains 16 or more received ARINC words. The HF1 (HF2) pin is
intended to act as an interrupt flag to the system’s external
microprocessor, allowing a 16 word data retrieval routine to be
performed, without the user needing to continually poll the HI-
3584A’s status register bits.
LABEL RECOGNITION
The chip compares the incoming label to the stored labels if label
recognition is enabled. If a match is found, the data is processed.
If a match is not found, no indicators of receiving ARINC data are
presented. Note that 00(Hex) is treated in the same way as any
other label value. Label bit significance is not changed by the
status of control register bit CR15. Label bits BD00-BD07 are
always compared to received ARINC bits 1 -8 respectively.
LOADING LABELS
After a write that takes CR1 from 0 to 1, the next 16 writes of data
(PL pulsed low) load label data into each location of the label
memory from the BD00 - BD07 pins. The PL1 pin is used to write
label data for receiver 1 and PL2 for receiver 2. Note that ARINC
word reception is suspended during the label memory write
sequence.
READING LABELS
After the write that changes CR1 from 0 to 1, the next 16 data
reads of the selected receiver (EN taken low) are labels. EN1 is
used to read labels for receiver 1, and EN2 to read labels for
receiver 2. Label data is presented on BD00 - BD07.
When writing to, or reading from the label memory, SEL must be a
one, all 16 locations should be accessed, and CR1 must be
written to zero before returning to normal operation. Label
recognition must be disabled (CR2/3=0) during the label read
sequence.
TRANSMITTER
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word (or 32 bit word if CR4=0) in the next available
position of the FIFO. If TX/R, the transmitter ready flag is high
(FIFO empty), then up to 32 words, each 31 or 32 bits long, may
be loaded. If TX/R is low, then only the available positions may be
loaded. If all 32 positions are full, the FFT flag is asserted and the
FIFO ignores further attempts to load data.
A transmitter FIFO half-full flag HFT is provided. When the
transmit FIFO contains less than 16 words, HFT is high,
indicating to the system microprocessor that a 16 ARINC word
block write sequence can be initiated.
In normal operation (CR4=1), the 32nd bit transmitted is a parity
bit. Odd or even parity is selected by programming control
register bit CR12 to a zero or one. If CR4 is programmed to a 0,
then all 32-bits of data loaded into the transmitter FIFO are
treated as data and are transmitted.
CR4,12
32 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
PARITY
GENERATOR
DATA AND
NULL TIMER
SEQUENCER
429DO
429DO
32 x 32 FIFO
DATA BUS
WORD CLOCK
ADDRESS
LOAD
BIT
AND
WORD GAP
COUNTER
START
SEQUENCE
WORD COUNTER
AND
FIFO CONTROL
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
DATA
CLOCK
CR13
DATA CLOCK
DIVIDER
FIGURE 3. TRANSMITTER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
6
TX/R
HFT
FFT
ENTX
PL1
PL2
CLK
TX CLK

6 Page



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共有リンク

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部品番号部品説明メーカ
HI-3584

3.3V Serial Transmitter and Dual Receiver

HOLTIC
HOLTIC
HI-3584A

ARINC 429 3.3V Serial Transmitter and Dual Receiver

HOLTIC
HOLTIC


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