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HI-3593 の電気的特性と機能

HI-3593のメーカーはHOLTICです、この部品の機能は「3.3V ARINC 429 Dual Receiver / Single Transmitter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI-3593
部品説明 3.3V ARINC 429 Dual Receiver / Single Transmitter
メーカ HOLTIC
ロゴ HOLTIC ロゴ 




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HI-3593 Datasheet, HI-3593 PDF,ピン配置, 機能
August 2013
HI-3593
3.3V ARINC 429 Dual Receiver,
Single Transmitter with SPI Interface
GENERAL DESCRIPTION
PIN CONFIGURATIONS (Top View)
The HI-3593 from Holt Integrated Circuits is a CMOS
integrated circuit for interfacing a Serial Peripheral
Interface (SPI) enabled microcontroller to the ARINC 429
serial bus. The device provides two receivers, each with
user-programmable label recognition for any combination
of 256 possible labels, 32 x 32 Receive FIFO, 3 priority-
label quick-access double-buffered registers and analog
line receiver. The independent transmitter has a 32 x 32
Transmit FIFO and built-in line driver. The line driver
operates from a single 3.3V supply and includes on-chip
DC/DC converter to generate the bipolar ARINC 429
differential voltage levels needed to directly drive the
ARINC 429 bus. The status of the transmit and receive
FIFOs and priority-label buffers can be monitored using
the programmable external interrupt pins, or by polling the
HI-3593 Status Registers. Other features include a
programmable option of data or parity in the 32nd bit, and
the ability to switch the bit-signifiance of ARINC 429 labels.
Pins are available with different input resistance and
output resistance values which provides flexibility when
using external lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V operation.
The HI-3593 applies the ARINC 429 protocol to the
receivers and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
FEATURES
· ARINC 429 specification compliant
· Single 3.3V power supply
· On-chip analog line driver and receiver connect
directly to ARINC 429 bus
· Programmable label recognition for 256 labels
· 32 x 32 Receive FIFOs and Priority-Label buffers
· Independent data rates for Transmit and Receive
· 10MHz, four-wire Serial Peripheral Interface (SPI)
· Industrial & extended temperature ranges
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PCI
HI-3593PCT
HI-3593PCM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
-1
RIN1A-40 - 2
RIN1A - 3
RIN1B - 4
RIN1B-40 - 5
RIN2A-40 - 6
RIN2A - 7
RIN2B - 8
RIN2B-40 - 9
MR - 10
ACLK - 11
HI-3593PQI
HI-3593PQT
HI-3593PQM
33 - AMPA
32 - TXAOUT
31 - AMPB
30 - TXBOUT
29 -
28 - TFULL
27 - TEMPTY
26 - R1FLAG
25 - R1INT
24 - R2FLAG
23 - R2INT
44 - Pin Plastic Quad Flat Pack (PQFP)
(DS3593 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/13

1 Page





HI-3593 pdf, ピン配列
HI-3593
PIN DESCRIPTIONS
SIGNAL
RIN1A-40
RIN1A
RIN1B
RIN1B-40
RIN2A-40
RIN2A
RIN2B
RIN2B-40
MR
ACLK
CS
SI
SCLK
SO
GND
MB1-1
MB1-2
MB1-3
MB2-1
MB2-2
MB2-3
R2INT
R2FLAG
R1INT
R1FLAG
TEMPTY
TFULL
TXBOUT
AMPB
TXAOUT
AMPA
V-
CN-
CN+
V+
CP-
CP+
VDD
FUNCTION
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
CONVERTER
POWER
DESCRIPTION
INTERNAL PULL UP / DOWN
Alternate ARINC receiver 1 positive input. Requires external 40K ohm resistor
ARINC receiver 1 positive input. Direct connection to ARINC 429 bus
ARINC receiver 1 negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver 1 negative input. Requires external 40K ohm resistor
Alternate ARINC receiver 2 positive input. Requires external 40K ohm resistor
ARINC receiver 2 positive input. Direct connection to ARINC 429 bus
ARINC receiver 2 negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver 2 negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags 50K ohm pull-down
Master timing source for the ARINC 429 receiver and transmitter
50K ohm pull-down
Chip Select. Data is shifted into SI and out of SO when CS is low.
50K ohm pull-up
SPI interface serial data input
50K ohm pull-down
SPI Clock. Data is shifted into or out of the SPI interface using SCK
50K ohm pull-down
SPI interface serial data output
Chip 0V supply
Goes high when Receiver 1, Priority-Label Mail Box 1 contains a message
Goes high when Receiver 1, Priority-Label Mail Box 2 contains a message
Goes high when Receiver 1, Priority-Label Mail Box 3 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 1 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 2 contains a message
Goes high when Receiver 2, Priority-Label Mail Box 3 contains a message
Receiver 2 programmable Interrupt pin
Goes high as defined by Flag / Interrupt Assignment Register
Receiver 1 programmable Interrupt pin
Goes high as defined by Flag / Interrupt Assignment Register
Goes high when the Transmit FIFO is empty
Goes high when the Transmit FIFO contains the maximum 32 ARINC 429 words
ARINC line driver negative output. Direct connection to ARINC 429 bus
Alternate ARINC line driver negative output. Requires external 32.5 ohm resistor
ARINC line driver positive output. Direct connection to ARINC 429 bus
Alternate ARINC line driver positive output. Requires external 32.5 ohm resistor
DC/DC negative voltage output
DC/DC converter fly capacitor for V-
DC/DC converter fly capacitor for V-
DC/DC positive voltage output
DC/DC converter fly capacitor for V+
DC/DC converter fly capacitor for V+
Chip 3.3V supply
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI-
3593. When CS goes low, the next 8 clocks at the SCK pin shift an
instruction op code into the decoder, starting with the first rising
edge. The op code is fed into the SI pin, most significant bit first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 8-bit Control Register writes, 32-
bit ARINC label writes or 256-bit writes to a channel’s label-
matching enable/disable memory.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
the data field bit-length varies with read instruction type.
SPI Instructions are of a common format. The first bit specifies
whether the instruction is a write “0” or read “1” transfer. The next
five bits specify the source or destination of the associated data
byte(s), and the last two bits are “don’t care”.
Source /
Destination
XX
MSB 7 6 5 4 3 2 1 0 LSB
SPI INSTRUCTION FORMAT
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-3593 電子部品, 半導体
HI-3593
RECEIVE STATUS REGISTER
(Receiver 1 Read, SPI Op-code 0x90)
(Receiver 2 Read, SPI Op-code 0xB0)
00
76543210
MSB
LSB
Bit Name
7X
6X
5 PL3
4 PL2
3 PL1
2 FFFULL
1 FFHALF
0 FFEMPTY
R/W Default Description
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 This bit is set when a message is received by Priority Label filter #3
R 0 This bit is set when a message is received by Priority Label filter #2
R 0 This bit is set when a message is received by Priority Label filter #1
R 0 This bit is set when the Receive FIFO contains 32 ARINC 429 messages
R 0 This bit is set when the Receive FIFO contains at least 16 ARINC 429 messages
R 1 This bit is set when the Receive FIFO is empty
TRANSMIT STATUS REGISTER
(Read, SPI Op-code 0x80)
00000
76543210
MSB
LSB
Bit Name
7X
6X
5X
4X
3X
2 TFFULL
1 TFHALF
0 TFEMPTY
R/W Default Description
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 Not used. Always reads “0”
R 0 This bit is set when the Transmit FIFO contains 32 ARINC 429 messages
R 0 This bit is set when the Transmit FIFO contains at least 16 ARINC 429 messages
R 1 This bit is set when the Transmit FIFO is empty
ACLK DIVISION REGISTER
(Write, SPI Op-code 0x38)
(Read, SPI Op-code 0xD4)
000
0
76543210
MSB
LSB
Bit Name
7X
6X
5X
4 - 1 DIV[3:0]
0X
R/W Default Description
R/W 0 Not used.
R/W 0 Not used.
R/W 0 Not used.
R/W 0 The value programmed in DIV[3:0] sets the ACLK division ratio (see table 2)
R/W 0 Not used.
HOLT INTEGRATED CIRCUITS
6

6 Page



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共有リンク

Link :


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