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HI-3597 の電気的特性と機能

HI-3597のメーカーはHOLTICです、この部品の機能は「Octal ARINC 429 Receivers」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI-3597
部品説明 Octal ARINC 429 Receivers
メーカ HOLTIC
ロゴ HOLTIC ロゴ 




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HI-3597 Datasheet, HI-3597 PDF,ピン配置, 機能
January, 2012
HI-3596, HI-3597, HI-3598, HI-3599
Octal ARINC 429 Receivers
with Label Recognition and SPI Interface
GENERAL DESCRIPTION
The HI-359x family from Holt Integrated Circuits are sili-
con gate CMOS ICs for interfacing up to eight ARINC
429 receive buses to a high-speed Serial Peripheral
Interface (SPI) enabled microcontroller. Each receiver
has user-programmable label recognition for up to 16
labels, a four-word data buffer (FIFO), and an on-chip
analog line receiver. Receive FIFO status can be moni-
tored using the programmable external interrupt pins,
or by polling the status register. Other features include
the ability to switch the bit-signifiance of the ARINC 429
label and to recognize the 32nd received ARINC bit as
either data or a parity flag. Some versions provide a digi-
tal transmit channel which can be utilized with an exter-
nal line driver such as HI-8570 to relay information from
multiple sources, for example sensors, to a single col-
lection point such as a flight computer and can also be
configured as a loopback test register for each receive
channel. Versions are also available with different input
resistance values to provide flexibility when using exter-
nal lightning protection circuitry. The SPI and all control
signals are CMOS and TTL compatible and support
3.3V or 5V operation.
32nd bit can be data or parity
Low Power
Industrial & extended temperature ranges
PIN CONFIGURATION (TOP VIEW)
ACLK - 1
SC__K - 2
CS - 3
SI - 4
SO - 5
MR - 6
TX1 - 7
TX0 - 8
RIN1A - 9
RIN1A-40 - 10
RIN1B-40 - 11
RIN1B - 12
- 13
HI-3598PQI
&
HI-3598PQT
39 - RIN8A
38 - RIN7B
37 - RIN7B-40
36 - RIN7A-40
35 - RIN7A
34 - RIN6B
33 - RIN6B-40
32 - RIN6A-40
31 - RIN6A
30 - RIN5B
29 - RIN5B-40
28 - RIN5A-40
27 - RIN5A
The HI-3596 and HI-3598 are full featured parts. The
HI-3597 and HI-3599 give the user the option of utilizing
a smaller 24-pin SOIC package with very little trade off in
features. In this case, a global interrupt flag is provided
instead of individual external FIFO interrupt pins. The
HI-3597 is identical to the HI-3599 except that it offers
the digital transmit feature and seven receive channels.
HI-3598 Full function, full pin-out version
52 - Pin Plastic Quad Flat Pack (PQFP)
FEATURES
ARINC 429 compliant
Up to 8 independent receive channels
Digital transmit channel (except HI-3599)
3.3V or 5.0V logic supply operation
On-chip analog line receivers connect directly to
ARINC 429 bus
Programmable label recognition for 16 labels per
channel
Independent data rate selection for each receiver
Four-wire SPI interface
Label bit-order control
ACLK - 1
SCK - 2
CS - 3
SI - 4
SO - 5
TX1 - 6
TX0 - 7
RIN2A - 8
RIN2B - 9
RIN3A - 10
RIN3B - 11
GND - 12
HI-3597
PSI
&
HI-3597
PST
24 - VDD
23 - FLAG
22 - RIN8B
21 - RIN8A
20 - RIN7B
19 - RIN7A
18 - RIN6B
17 - RIN6A
16 - RIN5B
15 - RIN5A
14 - RIN4B
13 - RIN4A
HI-3597 minimum footprint, reduced pin-out version
24 - Pin Plastic Small Outline package (SOIC)
(See page 13 for additional package pin configurations)
DS3598 Rev. C
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
01/12

1 Page





HI-3597 pdf, ピン配列
HI-3596, HI-3597, HI-3598, HI-3599
PIN DESCRIPTIONS
Table 1.  Pin Descriptions
Pin Function Description
3596 3597 3598 3599
VDD
POWER 3.3V or 5.0V power supply
XXXX
GND
POWER Chip 0V supply
XXXX
CS
INPUT
Chip select. Data is shifted into SI and out of SO when
CS is low
X
X
X
X
SCK
INPUT
SPI Clock. Data is shifted into or out of the SPI interface
using SCK
X
X
X
X
SI INPUT SPI interface serial data input
XXXX
SO OUTPUT SPI interface serial data output
XXXX
ACLK
INPUT
Master 1 MHz timing reference for the ARINC 429
receiver and transmitter
X
X
X
X
RIN1A* - RIN8A
ARINC
INPUT
ARINC receiver positive input. Direct connection to
ARINC 429 bus
Std
Std
X
Std
RIN1B* - RIN8B
ARINC
INPUT
ARINC receiver negative input. Direct connection to
ARINC 429 bus
Std
Std
X
Std
RIN1A-40* - RIN8A-40
ARINC
INPUT
Alternate ARINC receiver positive input. Requires
external 40KΩ resistor
-40
-40
X
-40
RIN1B-40* - RIN8B-40
ARINC
INPUT
Alternate ARINC receiver negative input. Requires
external 40KΩ resistor
-40
-40
X
-40
FLAG1 - FLAG8
OUTPUT
Goes high when ARINC 429 receiver FIFO is not empty
(CR1=0), or full (CR1=1)
X
-
X
-
FLAG
OUTPUT Logical OR of FLAG1 through FLAG8
XXXX
TX1
OUTPUT ARINC 429 test word ONE state serial output pin
XXX
-
TX0
OUTPUT ARINC 429 test word ZERO state serial output pin
XXX
-
Hardware active high Master Reset. Clears all
MR INPUT receivers and FIFOs. Does not affect Control Register X - X -
contents.
* NOTE: RIN1A & RIN1B are not available on HI-3597
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-3597 電子部品, 半導体
HI-3596, HI-3597, HI-3598, HI-3599
ARINC 429 Data Format
Control Register bit CR9 controls how individual bits in
the received ARINC word are mapped to the HI-359x
SPI data word during data read operations. Table 5
describes this mapping.
Table 5.  SPI / ARINC bit-mapping
SPI / ARINC bit-mapping
SPI Order 1 2 - 22 23 24 25 26 27 28 29 30 31 32
ARINC bit 32 31 - 11 10 9 1 2 3 4 5 6 7 8
CR9 = 0
Data
ARINC bit 32 31 - 11 10 9 8 7 6 5 4 3 2 1
CR9 = 1
Data
RINA-40
RINA
RINB
RINB-40
VDD
GND
VDD
GND
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONE
NULL
ZERO
Figure 3.  ARINC Receiver Input
The HI-359x family guarantees recognition of these lev-
els with a common mode Voltage with respect to GND
less than ±30V for the worst case condition (3.15V sup-
ply and 13V signal level).
The tolerances in the design guarantee detection of
the above levels, so the actual acceptance ranges are
slightly larger. If the ARINC signal is out of the actual
acceptance ranges, including the nulls, the chip rejects
the data.
ARINC 429 Receiver
ARINC Bus Interface
Figure 3 shows the input circuit for each on-chip ARINC
429 line receiver. The ARINC 429 specification requires
detection levels summarized in Table 6.
Receiver Logic Operation
Figure 4 is a block diagram showing the logic for each
receiver.
Bit Timing
The ARINC 429 specification defines timing tolerances
for received data according to Table 7.
Table 7.  ARINC 429 Receiver Timing Tolerances
Table 6.  ARINC 429 Detection Levels
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
Bit Rate
Pulse Rise Time
Pulse Fall Time
Pulse Width
HIGH SPEED
100Kbps ± 1%
1.5 ± 0.5μs
1.5 ± 0.5μs
5μs ± 5%
LOW SPEED
12K - 14.5Kbps
10 ± 5μs
10 ± 5μs
34.5 to 41.7μs
HOLT INTEGRATED CIRCUITS
6

6 Page



ページ 合計 : 18 ページ
 
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共有リンク

Link :


部品番号部品説明メーカ
HI-3593

3.3V ARINC 429 Dual Receiver / Single Transmitter

HOLTIC
HOLTIC
HI-3596

Octal ARINC 429 Receivers

HOLTIC
HOLTIC
HI-3597

Octal ARINC 429 Receivers

HOLTIC
HOLTIC
HI-3598

Octal ARINC 429 Receivers

HOLTIC
HOLTIC


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