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PDF 8V43FS92432 Data sheet ( Hoja de datos )
| Número de pieza | 8V43FS92432 | |
| Descripción | 1360MHz Dual Output LVPECL Clock Synthesizer | |
| Fabricantes | IDT | |
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1360MHz Dual Output LVPECL
Clock Synthesizer
8V43FS92432
DATA SHEET
General Description
The 8V43FS92432 is a 3.3V-compatible, PLL based clock
synthesizer targeted for high performance clock generation in
mid-range to high-performance telecom, networking, and computing
applications. With output frequencies from 21.25MHz to 1360MHz
and the support of two differential PECL output signals, the device
meets the needs of the most demanding clock applications.
The 8V43FS92432 is a programmable high-frequency clock source
(clock synthesizer). The internal PLL generates a high-frequency
output signal based on a low-frequency reference signal. The
frequency of the output signal is programmable and can be changed
on the fly for frequency margining purpose.
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. Alternatively, a LVCMOS compatible
clock signal can be used as a PLL reference signal. The frequency of
the internal crystal oscillator is divided by a selectable divider and
then multiplied by the PLL. Its output is scaled by a divider that is
configured by either the I2C or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider
M, and the PLL post-divider N determine the output frequency. The
feedback path of the PLL is internal.
The PLL post-divider N is configured through either the I2C or the
parallel interfaces, and can provide one of six division ratios (2, 4, 8,
16, 32, 64). This divider extends the performance of the part while
providing a 50% duty cycle. The high-frequency outputs, QA and QB,
are differential and are capable of driving a pair of transmission lines
terminated 50 to VCC – 2.0 V. The second high-frequency output,
QB, can be configured to run at either 1x or 1/2x of the clock
frequency or the first output (QA). The positive supply voltage for the
internal PLL is separated from the power supply for the core logic
and output drivers to minimize noise induced jitter.
The configuration logic has two sections: I2C and parallel. The
parallel interface uses the values at the M[9:0], NA[2:0], NB, and P
parallel inputs to configure the internal PLL dividers. The parallel
programming interface has priority over the serial I2C interface. The
serial interface is I2C compatible and provides read and write access
to the internal PLL configuration registers. The lock state of the PLL
is indicated by the LVCMOS-compatible LOCK output.
Features
• 21.25MHz to 1360MHz synthesized clock output signal
• Two differential, LVPECL-compatible high-frequency outputs
• Output frequency programmable through 2-wire I2C bus or
parallel interface
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference clock input
• Synchronous clock stop functionality for both outputs
• LOCK indicator output (LVCMOS)
• LVCMOS compatible control inputs
• Fully integrated PLL
• 3.3-V power supply
• 48-lead LQFP
• 48-lead Pb-free package available
• SiGe Technology
• Ambient temperature range: –40°C to +85°C
Applications
• Programmable clock source for server, computing, and
telecommunication systems
• Frequency margining
• Oscillator replacement
8V43FS92432 REVISION 1 10/28/15
1 ©2015 INTEGRATED DEVICE TECHNOLOGY, INC.
1 page  
8V43FS92432 DATA SHEET
Table 3. Function Table
Control
Default1
0
1
REF_SEL
M[9:0]
NA[2:0]
NB
P
nPLOAD
ADR[1:0]
SDA, SCL
nBYPASS
TEST_EN
nCLK_STOP[A:B]
nMR
Inputs
1 Selects REF_CLK input as PLL reference clock Selects the XTAL interface as PLL reference clock
01 1111 0100b2
PLL feedback divider (10-bit) parallel programming interface
010 PLL post-divider parallel programming interface. See Table 10
0 PLL post-divider parallel programming interface. See Table 11
1 PLL pre-divider parallel programming interface. See Table 9
Selects the parallel programming interface. The
0
internal PLL divider settings (M, NA, NB and P)
are equal to the setting of the hardware pins.
Leaving the M, NA, NB and P pins open (floating)
results in a default PLL configuration with fOUT =
Selects the serial (I2C) programming interface. The
internal PLL divider settings (M, NA, NB and P) are
set and read through the serial interface.
250MHz. See application/programming section.
00 Address Bit = 0
Address Bit = 1
See Programming the 8V43FS92432
PLL function bypassed
1 fQA = fREF ÷ NA and
fQB = fREF÷ (NA · NB)
0 Application Mode. Test mode disabled.
PLL function enabled:
fQA = (fREF ÷ P) · M ÷ NA and
fQB = (fREF ÷ P) · M ÷ (NA · NB)
Factory test mode is enabled
Output Qx is disabled in logic low state.
1
Synchronous disable is only guaranteed if
Output Qx is synchronously enabled
NB = 0.
The device is reset. The output frequency is zero
and the outputs are asynchronously forced to
logic low state.
After releasing reset (upon the rising edge of
nMR and independent on the state of nPLOAD),
the 8V43FS92432 reads the parallel interface (M,
NA, NB and P) to acquire a valid startup
frequency configuration.
See application/programming section.
The PLL attempts to lock to the reference signal.
The tLOCK specification applies.
Outputs
LOCK
PLL is not locked
NOTE 1. Default states are set by internal input pull-up or pull-down resistors of 75k
NOTE 2. If fREF = 16MHz, the default configuration will result in a output frequency of 250MHz.
PLL is frequency locked
REVISION 1 10/28/15
5 1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
5 Page 
8V43FS92432 DATA SHEET
Programming the 8V43FS92432
The 8V43FS92432 has a parallel and a serial configuration
interface. The purpose of the parallel interface is to directly configure
the PLL dividers through hardware pins without the overhead of a
serial protocol. At device startup, the device always obtains an initial
PLL frequency configuration through the parallel interface. The
parallel interface does not support reading the PLL configuration.
The serial interface is I2C compatible. It allows reading and writing
devices settings by accessing internal device registers. The serial
interface is designed for host-controller access to the synthesizer
frequency settings for instance in frequency-margining applications.
nPLOAD = 0 disables the I2C-write-access to the configuration
registers and any data written into the register is ignored. However,
the 8V43FS92432 is still visible at the I2C interface and I2C transfers
are acknowledged by the device. Read-access to the internal
registers during nPLOAD = 0 (parallel programming mode) is
supported.
Note that the device automatically obtains a configuration using the
parallel interface upon the release of the device reset (rising edge of
nMR) and independent on the state of nPLOAD. Changing the state
of the nPLOAD input is not supported when the device performs any
transactions on the I2C interface.
Using the Parallel Interface
The parallel interface supports write-access to the PLL frequency
setting directly through 15 configuration pins (P, M[9:0], NA[2:0], and
NB). The parallel interface must be enabled by setting nPLOAD to
logic low level. During nPLOAD = 0, any change of the logical state
of the P, M[9:0], NA[2:0], and NB pins will immediately affect the
internal PLL divider settings, resulting in a change of the internal
VCO-frequency and the output frequency. The parallel interface
mode disables the I2C write-access to the internal registers;
however, I2C read-access to the internal configuration registers is
enabled.
Upon startup, when the device reset signal is released (rising edge
of the nMR signal), the device reads its startup configuration through
the parallel interface and independent on the state of nPLOAD. It is
recommended to provide a valid PLL configuration for startup. If the
parallel interface pins are left open, a default PLL configuration will
be loaded. After the low-to-high transition of nPLOAD, the
configuration pins have no more effect and the configuration
registers are made accessible through the serial interface.
Table 12. PLL Feedback-Divider Configuration (M)
Feedback
Divider M 9 8 7 6 5 4 3 2 1 0
Pin M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
Default 0 1 1 1 1 1 0 1 0 0
Programming Model and Register Set
The synthesizer contains two fully accessible configuration registers
(PLL_L and PLL_H) and a write-only command register (CMD).
Programming the synthesizer frequency through the I2C interface
requires two steps: 1) writing a valid PLL configuration to the
configuration registers and 2) loading the registers into the PLL by
an I2C command. The PLL frequency is affected as a result of the
second step. This two-step procedure can be performed by a single
I2C transaction or by multiple, independent I2C transactions. An
alternative way to achieve small PLL frequency changes is to use
the increment or decrement commands of the synthesizer, which
have an immediate effect on the PLL frequency.
Synthesizer – PLL
PN
M
LOAD/GET
Configuration Latches
PLL_L (R/W) PLL_H (R/W) CMD (W)
0x00 0x01
0xF0
I2C Registers
I2C Access
Figure 1. . I2C Mode Register Set
Figure 1. illustrates the synthesizer register set. PLL_L and PLL_H
store a PLL configuration and are fully accessible (Read/Write) by
the I2C bus. CMD (Write only) accepts commands (LOAD, GET, INC,
DEC) to update registers and for direct PLL frequency changes.
Table 13. PLL Pre/Post-Divider Configuration (N, P)
Post-Div
Post-Div
Pre-Div
NA 2 1 0
NB NB
PP
Pin NA2 NA1 NA0
Pin NB
Pin P
Set the synthesizer frequency:
1) Write the PLL_L and PLL_H registers with a new configura-
tion (see Table 15 and Table 16 for register maps)
2) Write the LOAD command to update the PLL dividers by the
current PLL_L, PLL_H content.
Default 0 1 0 Default 0 Default 1
Using the I2C Interface
nPLOAD = 1 enables the programming and monitoring of the
internal registers through the I2C interface. Device register access
(write and read) is possible through the 2-wire interface using SDA
(configuration data) and SCL (configuration clock) signals. The
8V43FS92432 acts as a slave device at the I2C bus. For further
information on I2C it is recommended to refer to the I2C bus
specification (version 2.1).
Read the synthesizer frequency:
1) Write the GET commands to update the PLL_L, PLL_H reg-
isters by the PLL divider setting
2) Read the PLL_L, PLL_H registers through I2C
Change the synthesizer frequency in small steps:
1) Write the INC or DEC command to change the PLL frequen-
cy immediately. Repeat at any time if desired.
REVISION 1 10/28/15
11 1360MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
11 Page | ||
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