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CN8236のメーカーはMindspeedです、この部品の機能は「ATM ServiceSAR Plus」です。 |
部品番号 | CN8236 |
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部品説明 | ATM ServiceSAR Plus | ||
メーカ | Mindspeed | ||
ロゴ | |||
このページの下部にプレビューとCN8236ダウンロード(pdfファイル)リンクがあります。 Total 30 pages
CN8236
ATM ServiceSAR Plus with xBR Traffic Management
The CN8236 Service Segmentation and Reassembly Controller integrates ATM terminal
functions, PCI Bus Master and Slave controllers, and a UTOPIA level 1 or 2 interface
with service-specific functions in a single package for AAL0, 3/4, and 5 operations.
The ServiceSAR Controller generates and terminates ATM traffic and automatically
schedules cells for transmission. The CN8236 is targeted at 155 Mbps throughput
systems where the number of VCCs is relatively large, or the performance of the overall
system is critical. Examples of such networking equipment include Routers, Ethernet
switches, ATM Edge switches, or Frame Relay switches.
Service-Specific Performance Accelerators
The CN8236 incorporates numerous service-specific features designed to accelerate
and enhance system performance. As examples, the CN8236 implements Echo
Suppression of LAN traffic via LECID filtering, and supports Frame Relay DE to CLP
interworking.
Advanced xBR Traffic Management
The xBR Traffic Manager in the CN8236 supports multiple ATM service categories. This
includes CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed Frame
Rate), and ABR. The CN8236 manages each VCC independently. It dynamically
schedules segmentation traffic to comply with up to 16+CBR user-configured
scheduling priorities for the various traffic classes. Scheduling is controlled by a
Schedule table configured by the user and based on a user-specified time reference.
ABR channels are managed in hardware according to user-programmable ABR
templates. These templates tune the performance of the CN8236’s ABR algorithms to a
specific system’s or network’s requirements.
–Continued–
Distinguishing Features
Service-Specific Performance
Accelerators
• LECID filtering and echo suppression
• Dual leaky bucket based on CLP
(frame relay)
• Frame relay DE interworking
• Internal SNMP MIB counters
• IP over ATM; supports both CLP0+1
and ABR shaping
Flexible Architectures
• Multi-peer host
• Direct switch attachment via reverse
UTOPIA
• ATM terminal
– Host control
– Local bus control
• Optional local processor
–Continued–
Functional Block Diagram
Timer
Counters
Multi-client
PCI Bus
PCI DMA
Master/ Co-
Slave Proc'r
Local Bus
Local Memory
Interface
Control/
Status
Reassembly
Coprocessor
Segmentation
Coprocessor
Cell
FIFO
UTOPIA
Master/Slave
Rx/Tx
CBR, VBR, ABR,
UBR, GFR
CN8236
Traffic Manager
Patent Pending
CN8250
PHY
Device
Data Sheet
28236-DSH-001-B
May 2003
1 Page –Continued from Front–
Multi-Queue Segmentation Processing
The CN8236’s segmentation coprocessor generates ATM cells for up to 64 K VCCs. The segmentation coprocessor
formats cells on each channel according to segmentation VCC tables, utilizing up to 32 independent transmit queues
and reporting segmentation status on a parallel set of up to 32 segmentation status queues. The segmentation
coprocessor fetches client data from the host, formats ATM cells while generating and appending protocol overhead,
and forwards these to the UTOPIA port. The segmentation coprocessor operates as a slave to the xBR Traffic Manager
which schedules VCCs for transmission.
Multi-Queue Reassembly Processing
The CN8236’s reassembly coprocessor stores the payload data from the cell stream received by the UTOPIA port into
host data buffers. Using a dynamic lookup method which supports NNI or UNI addressing, the reassembly coprocessor
processes up to 64 K VCCs simultaneously. The host supplies free buffers on up to 32 independent free buffer queues,
and the reassembly coprocessor performs all CPCS protocol checks and reports the results of these checks as well as
other status data on one of 32 independent reassembly status queues.
High Performance Host Architecture with Buffer Isolation
The CN8236 host interface architecture maximizes performance and system flexibility. The device’s control and status
queues enable host/SAR communication via write operations alone. This write-only architecture lowers latency and PCI
bus occupancy. Flexibility is achieved by supporting a scalable peer-to-peer architecture. Multiple host clients can be
addressed by the segmentation and reassembly (SAR) as separate physical or logical PCI peers. Segmentation and
reassembly data buffers on the host system are identified by buffer descriptors in SAR-shared (or host) memory which
contain pointers to buffers. The use of buffer descriptors in this way allows for isolation of data buffers from the
mechanisms that handle buffer allocation and linking. This provides a layer of indirection in buffer assignment and
management that maximizes system architecture flexibility.
Designer Toolkit
Mindspeed provides an evaluation environment for the CN8236/RS8254EVM which provides a working reference
design, an example of a software driver, and facilities for generating and terminating all service categories of ATM
traffic. This system accelerates ATM system development by providing a rapid prototyping environment.
28236-DSH-001-B
Mindspeed Technologies™
3Pages 28236-DSH-001-B
Mindspeed Technologies™
6 Page | |||
ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ CN8236 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
CN8236 | ATM ServiceSAR Plus | Mindspeed |