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850S1201 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 850S1201
部品説明 12:1 Single-ended Multiplexer
メーカ IDT
ロゴ IDT ロゴ 



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850S1201 Datasheet, 850S1201 PDF,ピン配置, 機能
12:1 Single-ended Multiplexer
850S1201
Datasheet
General Description
The 850S1201 is a low skew12:1 Single-ended Clock Multiplexer.
The 850S1201 has 12 selectable single-ended clock inputs and 1
single- ended clock output. The device operates up to 250MHz and
is packaged in a 20 TSSOP package.
Features
12:1 single-ended multiplexer
Nominal output impedance: 20(VDD = 3.3V)
Maximum output frequency: 250MHz
Propagation delay: 2.7ns (maximum)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
CLK_SEL2 Pulldown
CLK_SEL3 Pulldown
CLK0 Pulldown
CLK1 Pulldown
CLK10 Pulldown
CLK11 Pulldown
OE Pullup
Q
©2016 Integrated Device Technology, Inc.
1
Pin Assignment
CLK8
CLK9
CLK10
CLK11
VDD
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
OE
1
2
3
4
5
6
7
8
9
10
20 CLK7
19 CLK6
18 CLK5
17 CLK4
16 CLK3
15 CLK2
14 CLK1
13 CLK0
12 GND
11 Q
850S1201
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm
package body
G Package
Top View
Revison B, February 8, 2016

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12:1 Single-ended Multiplexer

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