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831724 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 831724
部品説明 Differential Clock/Data Multiplexer
メーカ IDT
ロゴ IDT ロゴ 



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831724 Datasheet, 831724 PDF,ピン配置, 機能
Differential Clock/Data Multiplexer
831724
Datasheet
General Description
The 831724 is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has two differential, selectable clock/data inputs. The
selected input signal is distributed to four low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831724 is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831724 ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831724 supports the clock multiplexing and
distribution of PCI Express Generation 1, 2, and 3 clock signals.
Features
2:1 differential clock/data multiplexer with fanout
Two selectable, differential inputs
Each differential input pair can accept the following levels: HCSL,
LVDS, LVPECL.
Four differential HCSL outputs
Maximum input/output clock frequency: 350MHz
Maximum input/output data rate: 700Mb/s (NRZ)
LVCMOS interface levels for all control inputs
PCI Express Gen 1,2,3 jitter compliant
Input skew: 165ps (maximum)
Output skew: 175ps (maximum)
Part-to-part skew: 450ps (maximum)
Full 3.3V supply voltage
Available in lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Block Diagram
IREF
Pulldown
CLK0 Pullup/down
nCLK0 Pulldown
Pullup/down
CLK1
nCLK1 Pulldown
Pullup
Pullup
Pullup
Pullup
SEL
0
1
QA
nQA
QB
nQB
QC
nQC
QD
nQD
Pin Assignment
32 31 30 29 28 27 26 25
VDD 1
24 nc
nOED 2
23 nOEC
CLK0 3
22 nc
nCLK0 4
21 nc
CLK1 5
20 nc
nCLK1 6
19 nc
nOEA 7
18 SEL
VDD 8
17 nc
9 10 11 12 13 14 15 16
831724I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B November 16, 2016

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Differential Clock/Data Multiplexer

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