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8312I PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 8312I
部品説明 1-to-12 LVCMOS/LVTTL Fanout Buffer
メーカ IDT
ロゴ IDT ロゴ 



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8312I Datasheet, 8312I PDF,ピン配置, 機能
Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
8312I
Datasheet
General Description
The 8312I is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312I single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 8312I is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312I ideal for
high performance, single ended applications that also require a
limited output voltage.
Features
Twelve LVCMOS/LVTTL outputs
CLK input supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Output skew: 160ps (maximum)
Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN Pullup
CLK Pulldown
D
Q
LE
OE Pullup
12
Q[0:11]
©2015 Integrated Device Technology, Inc
1
Pin Assignment
GND
VDD
CLK_EN
CLK
GND
OE
VDD
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q4
VDDO
Q5
GND
Q6
VDDO
Q7
GND
8312I
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
December 14, 2015

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