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5PB1108CMGI の電気的特性と機能

5PB1108CMGIのメーカーはIDTです、この部品の機能は「1.8V to 3.3V LVCMOS High Performance Clock Buffer Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 5PB1108CMGI
部品説明 1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
メーカ IDT
ロゴ IDT ロゴ 




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5PB1108CMGI Datasheet, 5PB1108CMGI PDF,ピン配置, 機能
1.8V to 3.3V LVCMOS High Performance
Clock Buffer Family
5PB11xx
DATASHEET
Description
The 5PB11xx is a high-performance LVCMOS Clock Buffer
Family. It has best-in-class Additive Phase Jitter of 50fsec
RMS.
There are five different fan-out variations, 1:2 to 1:10,
available.
The IDT5PB11xx also supports a synchronous glitch-free
Output Enable function to eliminate any potential intermediate
incorrect output clock cycles when enabling or disabling
outputs. It comes in various packages and can operate from a
1.8V to 3.3V supply.
Features
High performance 1:2, 1:4, 1:6, 1:8, 1:10 LVCMOS clock
buffer
Very low pin-to-pin skew <50 ps
Very low additive jitter <50 fs
Supply voltage: 1.8V to 3.3V
fMAX = 200MHz
Integrated serial termination for 50ohm channel
Packaged in 8-, 14-, 16-, 20-pin TSSOP and small DFN
and QFN packages
Extended (-40°C to +105°C) temperature range
Block Diagram
CLKIN
LVCMOS
LVCMOS
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
Yn
1G
5PB11xx MAY 13, 2016
1 ©2016 Integrated Device Technology, Inc.

1 Page





5PB1108CMGI pdf, ピン配列
Pin Assignments for DFN/QFN Packages
CLKIN
1G
Y0
GND
18
27
3 5PB1102CMGI 6
45
Y1
NC
VDD
NC
CLKIN
1G
Y0
GND
18
27
5PB1104CMGI
36
45
Y1
Y3
VDD
Y2
Y0
GND
VDD
Y4
16 15 14 13
1 12
2 5PB1106CMGI11
3 10
49
5 6 78
VDD
Y2
GND
Y5
5PB11xx DATASHEET
Y0
GND
VDD
Y4
GND
20 19 18 17 16
1 15
2 14
3 5PB1110NDGI 13
4 12
5 11
6 7 8 9 10
Y2
GND
Y5
VDD
Y7
Y0
GND
VDD
Y4
16 15 14 13
1 12
2 5PB1108CMGI11
3 10
49
5 6 78
VDD
Y2
GND
Y5
Pin Descriptions for DFN/QFN Packages
Device Number
5PB1102CMGI
5PB1104CMGI
5PB1106CMGI
5PB1108CMGI
5PB1110NDGI
LVCMOS
Clock Input
CLKIN
1
1
15
15
19
Clock Output
Enable
1G
2
2
16
16
20
LVCMOS Clock Output
Y0, Y1, . . . Y9
3, 8
3, 5, 7, 8
1, 4, 9, 11, 13, 14
1, 4, 6, 7, 9, 11, 13, 14
1, 4, 6, 8, 10, 11, 13, 15, 17, 18
Output Logic Table
Supply Voltage
VDD
6
6
3, 8, 12
3, 8, 12
3, 7, 12, 16
Ground
GND
4
4
2, 5, 10
2, 5, 10
2, 5, 9, 14
CLKIN
X
L
H
Inputs
1G
L
H
H
Output
Yn
L
L
H
After at least three cycles of input clock toggling. Output Enable function is asynchronous to eliminate any intermediate incorrect output clock cycles during transition which may cause
frequency peaking to the downstream device.
MAY 13, 2016
3 1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY


3Pages


5PB1108CMGI 電子部品, 半導体
5PB11xx DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
0 200 MHz
Output Rise Time (2 pF load)
Output Fall Time (2 pF load)
Output Rise Time (5 pF load)
Output Fall Time (5 pF load)
Start-up Time
Propagation Delay
tOR
tOF
tOR
tOF
tSTART-UP
0.36V to 1.44V, CL=2 pF
1.44V to 0.36V, CL=2 pF
0.36V to 1.44V, CL=5 pF
1.44V to 0.36V, CL=5 pF
Part start-up time for valid outputs after VDD ramp-up
Note 1
0.5 0.75
0.5 0.75
0.8 1.0
0.8 1.0
3
1.9 2.2
ns
ns
ns
ns
ms
ns
Buffer Additive Phase Jitter, RMS
156.25MHz, Integration Range: 12kHz-20MHz
0.05 ps
Output to Output Skew (5PB1102/04/06)
Rising edges at VDD/2, Note 2
35 50 ps
Output to Output Skew (5PB1108/10)
Rising edges at VDD/2, Note 2
45 65 ps
Device to Device Skew
Rising edges at VDD/2
200 ps
Output Enable Time
Output Disable Time
tEN CL < 5 pF
tDIS CL < 5 pF
3 cycles
3 cycles
VDD = 2.5 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
0 200 MHz
Output Rise Time (2 pF load)
Output Fall Time (2 pF load)
Output Rise Time (5 pF load)
Output Fall Time (5 pF load)
Start-up Time
Propagation Delay
tOR
tOF
tOR
tOF
tSTART-UP
0.5V to 2.0V, CL=2 pF
2.0V to 0.5V, CL=2 pF
0.5V to 2.0V, CL=5 pF
2.0V to 0.5V, CL=5 pF
Part start-up time for valid outputs after VDD ramp-up
Note 1
0.4 0.7
0.4 0.7
0.75 1.0
0.75 1.0
3
2.4 2.9
ns
ns
ns
ns
ms
ns
Buffer Additive Phase Jitter, RMS
156.25MHz, Integration Range: 12kHz-20MHz
0.05 ps
Output to Output Skew (5PB1102/04/06)
Rising edges at VDD/2, Note 2
35 50 ps
Output to Output Skew (5PB1108/10)
Rising edges at VDD/2, Note 2
45 65 ps
Device to Device Skew
Rising edges at VDD/2
200 ps
Output Enable Time
Output Disable Time
tEN CL < 5 pF
tDIS CL < 5 pF
3 cycles
3 cycles
VDD = 3.3 V ±5%, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
0 200 MHz
Output Rise Time (2 pF load)
Output Fall Time (2 pF load)
Output Rise Time (5 pF load)
Output Fall Time (5 pF load)
Start-up Time
Propagation Delay
tOR
tOF
tOR
tOF
tSTART-UP
0.66V to 2.64V, CL=2 pF
2.64V to 0.66V, CL=2 pF
0.66V to 2.64V, CL= 5pF
2.64V to 0.66V, CL=5 pF
Part start-up time for valid outputs after VDD ramp-up
Note 1
0.45 0.6
0.45 0.6
0.7 1.0
0.7 1.0
3
2 2.4
ns
ns
ns
ns
ms
ns
Buffer Additive Phase Jitter, RMS
156.25MHz, Integration Range: 12kHz-20MHz
0.05 ps
Output to Output Skew (5PB1102/04/06)
Rising edges at VDD/2, Note 2
35 50 ps
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY
6
MAY 13, 2016

6 Page



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部品番号部品説明メーカ
5PB1108CMGI

1.8V to 3.3V LVCMOS High Performance Clock Buffer Family

IDT
IDT


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